I've just about finished laying out the first bank of DDR3 memory on the C6 Integra. We are using x16 memory and I have swapped around some of the data bits. I have currently gone outside of the byte lane, but stayed inside of the part, of course. For example, I swapped D0 and D12. D0 and D12 are in two different byte lanes, but inside the same DDR3 part and all of the traces for the part data lines and clocks are all equal (all 22 lines). Is this a violation on the C6 Integra?
I believe this centers around the DDR3 controller and whether it supports read-modify-write operations at the byte level. If this is the case, I need to ripup what I've done and redo it, keeping inside the byte-lane when swapping. I need an answer to this quickly if you can get it for me.
