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Original question:

DRA829J: ROM CODE use of MCU_Core_0 TCM's

DRA829J: LPSC SwDisable and Reset flag

Joao Simoes
Prodigy 215 points

Part Number: DRA829J

Tool/software:

Dear TI team,

What is the difference between the SwDisable and ResetFlag of the LSPC Modules?

While setting some cores LPSC modules SwDisable to Disable state, the LPSC is not transitioning state, we do not understand why.

  • 0
    TI__Mastermind 22250 points

    Joao, can you clarify where you are reading SwDisable and ResetFlag? I assume you are looking at the MDSTAT but I can't match your terminology.

    The LPSC is built so that if something is accessing the I, it will not shut down. This could be a cause. You could also try the FORCE bit.

  • 0 in reply to Kevin Lavery
    Prodigy 215 points

    Hi Kevin,

    Yes, your assumption of the MDSTAT is correct.

    I'm not sure about the cause.
    Could you mention what might be impeding turning OFF A72 LPSC core 0 for example?
    Beside the core itself, what other stuff might be keep the LPSC from transitioning it's state?

    I did try using the force bit and it did transition the LPSC.
    However, I would like not to force it, I would rather understand what might be behind of this.

    Thank you,
    João Simões

  • 0 in reply to Joao Simoes
    Prodigy 215 points

    Hi,

    Is there any update on the subject?

    Thank you,
    João Simões