TMS320C6657: TMS320C6657 SPI boot parameter table default values

KENGO AKIKAWA

Let me look at it and get back.

Regards

Shankari G

KENGO AKIKAWA

Target Frequency (MHz) =
 input_clock (MHz) * [(PLL1_M + 1)]/ (2 * (PLL1_D + 1) )

#define PLL1_M 19   ------> PLL Multiplier
#define PLL1_D 0     -------> PLL Divider.

Assume input clock is 100 MHz,

Target Frequency (MHz) = 100 * [19 +1 ] / ( 2 * ( 0 + 1) ) 

                                        = 100 * 20 / 2

                                        = 1000 MHz.

--

For SPI peripheral clock, page no:85 in the data sheet..https://www.ti.com/lit/ds/symlink/tms320c6657.pd

 • SYSCLK7: 1/6-rate clock for slow peripherals (GPIO, UART, Timer, I 2C, SPI, EMIF16, McBSP, and so forth.) and sources the SYSCLKOUT output pin.

Consider the SYSCLK is 1000 MHz,

==> 1000 MHz / 6 = 166.66 mHz ==== > SPI Clock.

--

For Direct SPI - BOOT, please refer this FAQ:- 

[FAQ] TMS320C6657: How to run the direct SPI-BOOT example on TI-C6657-EVM without IBL ? - Processors forum - Processors - TI E2E support forums

As per the Direct boot example code ( i.e.,  0435.C6657_directROM_Boot_example.zip  ) ,

the default values are given in the file spiboot.c

====================================

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
	BOOT_EMIF_ENABLE_SLSW_config6 | \
	BOOT_EMIF_ENABLE_SLSW_config7 | \
	BOOT_EMIF_ENABLE_SLSW_config8 | \
	BOOT_EMIF_ENABLE_SLSW_config9 | \
	BOOT_EMIF_ENABLE_SLSW_config10 | \
	BOOT_EMIF_ENABLE_SLSW_config18 | \
	BOOT_EMIF_ENABLE_SLSW_config19 | \
	BOOT_EMIF_ENABLE_SLSW_config20 | \
	BOOT_EMIF_ENABLE_SLSW_config22 | \
	BOOT_EMIF_ENABLE_SLSW_config12 | \
	BOOT_EMIF_ENABLE_SLSW_config23 | \
	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
    
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */

    0x62477AB2,  /* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x0000144F,  /* sdRamRefreshCtl  */
    0x1333780C,  /* sdRamTiming1 */
    0x30717FE3,  /* sdRamTiming2 */
    0x559F86AF,  /* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x0010010F,  /* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
    
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

----

If you are looking for a boot loader source code, you can download from here:- 

https://software-dl.ti.com/sdoemb/sdoemb_public_sw/rbl/1_0_C6657/index_FDS.html

Regards

Shankari G

Hi, Shankari-san,

<the default values are given in the file spiboot.c.

I couldn't find the default value of the SPI PARAMETR TABLE related to SPI in the file spiboot.c.

Please tell me the corresponding location in the file spiboot.c for each SPI BOOT PARAMETER I showed in my question.

Also, I think the SPI MODULE clock is 100MHz/6=16.666MHz.

(In the case of SPI boot, the PLL is bypassed)

What do you think?

Thanks and regards,

KENGO AKIKAWA 

How about the RBL source code? ( provided the link in my previous post ) 

By any chance, you downloaded and checked for the SPI boot parameter table?

Regards

Shankari G

KENGO AKIKAWA,

I understand that the BOOT PARAMETER TABLE used in the IBL would be similar to the one used in RBL.

So, please look at the default values of SPI BOOT Parameter table in the IBL source code enclosed in Processor SDK 6.3

The following is just the boot parameter table structure used in the IBL code.

typedef struct boot_params_spi_s
{
    /* common portion of the Boot parameters */
    UINT16 length;
    UINT16 checksum;
    UINT16 boot_mode;
    UINT16 portNum;
    UINT16 swPllCfg_msw;  /* CPU PLL configuration, MSW */
    UINT16 swPllCfg_lsw;  /* CPU PLL configuration, LSW */
    
    UINT16 options;
    /*
     * SPI Specific Options
     * Bit 01-00: BT:                                      
     *            00 - Boot Parameter Mode                            
     *            01 - Boot Table Mode                     
     *            10 - Boot Config mode
     *            11 - GP header blob
     * Other bits:  Reserved 
     */ 
     #define BOOT_PARAMS_SPI_OPTIONS_BP             0x0000
     #define BOOT_PARAMS_SPI_OPTIONS_BT             0x0001
     #define BOOT_PARAMS_SPI_OPTIONS_BC             0x0002
     #define BOOT_PARAMS_SPI_OPTIONS_GPHDR          0x0003
     
     #define BOOT_PARAMS_SPI_OPTIONS_MASK           0x0003
     #define BOOT_PARAMS_SPI_OPTIONS_SHIFT          0
     
     #define BOOT_PARAMS_SPI_IS_BOOTTBL_MODE(options) \
             (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BT)
             
     #define BOOT_PARAMS_SPI_IS_BOOTCONFIG_MODE(options) \
             (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BC)
             
     #define BOOT_PARAMS_SPI_IS_BOOTPARAM_MODE(options) \
             (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BP)
             
     #define BOOT_PARAMS_SPI_IS_GPHDR_MODE(options) \
             (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_GPHDR)
             
             
     #define BOOT_PARAMS_SPI_SET_BOOTTBL_MODE(options, mode)               \
             (options) = ((options) & ~BOOT_PARAMS_SPI_OPTIONS_MASK) |     \
                         (((mode)   &  BOOT_PARAMS_SPI_OPTIONS_MASK) <<    \
                                       BOOT_PARAMS_SPI_OPTIONS_SHIFT)
             
             
     UINT16 addrWidth;          /* 16 or 24 are the only valid values */
     UINT16 nPins;              /* 4 or 5 pins are the only valid values */
     UINT16 csel;               /* only values 0b10 (cs0 low) or 0b01 (cs1 low) are valid */
     UINT16 mode;               /* Clock phase/polarity. These are the standard SPI modes 0-3 */
     UINT16 c2tdelay;           /* Setup time between chip select assert and the transaction */
     
     UINT16 cpuFreqMhz;         /* Speed the CPU is running after PLL configuration */
     UINT16 busFreqMhz;         /* The speed of the SPI bus, the megahertz portion */
     UINT16 busFreqKhz;         /* The KHz portion of the bus frequency. A frequency of 1.5 MHz would have the value 5 here */
     
     UINT16 read_addr_msw;      /* The base address to read from the SPI, upper 16 bits */
     UINT16 read_addr_lsw;      /* The base address to read from the SPI, lower 16 bits */
     
     UINT16 next_csel;          /* The next chip select to use if in boot config mode, when the config is complete */
     UINT16 next_read_addr_msw; /* The next read address to use if in boot config mode */
     UINT16 next_read_addr_lsw; /* The next read address to use if in boot config mode */
             
} BOOT_PARAMS_SPI_T;     

In the initialization code, the default values will be given. 

So, please look at the default values of SPI BOOT Parameter table in the IBL source code enclosed in Processor SDK 6.3

PROCESSOR-SDK-RTOS-C665x 06_03_00_106
http://software-dl.ti.com/processor-sdk-rtos/esd/C665x/latest/index_FDS.html

Regards

Shankari G

Hi Shankari

I will try to check the default value in the RBL source code and IBL code.

Also, could you please answer my question from my previous post?

Thanks and regards,

KENGO AKIKAWA said:

I couldn't find the default value of the SPI PARAMETR TABLE related to SPI in the file spiboot.c.

For Direct SPI boot, those default values of EMIF table is sufficient from the user.

Because in the RBL it has the necessary value settings for SPI. 

That's why I pointed the values of EMIF table which encloses more on the DDR configuration settings/timing parameters etc.......

Please note for Direct-SPI boot, IBL is not needed / used.

During direct boot, after executing RBL, it jumps according to the boot mode and load the code directly without any IBL. 

KENGO AKIKAWA said:

Also, I think the SPI MODULE clock is 100MHz/6=16.666MHz.

(In the case of SPI boot, the PLL is bypassed)

Yes for SPI boot, PLL is bypassed.

but still, whatever is the SYSCLK you get, the SPI modules clock will be 1/6 th.

• SYSCLK7: 1/6-rate clock for slow peripherals (GPIO, UART, Timer, I 2C, SPI, EMIF16, McBSP, and so forth.) and sources the SYSCLKOUT output pin.

SYSCLK7 =  ( SYSCLK / 6 ) 

Whereas the SYSCLK is the DSP target frequency.

For more info refer the Figure 6-3. Main PLL and PLL Controller ----> Page no: 83 which gives the clear picture on PLL-Bypass.

======> 

Please note, if you use IBL, PLL is not bypassed. ( As we know, If IBL is used, that is, loading IBL from EEPROM, then it cannot be called as SPI boot ) 

I mean if you use IBL and then load the app-code from SPI-NOR.....

---

You can check the SPI clock by the below method.

1. Run the Direct SPI boot example I have pointed on TI-C6657 EVM.

2. Measure the SPI clock

3. Compare the measurement with your custom board.

--

As per the data sheet -------------------> page no:- 189 

The bus frequency programmed into the SPI by the boot ROM is from the table: MHz.kHz. So for a 5.1 MHz bus frequency the MHz value is 5, the kHz value is 100

It is set by the RBL.

You can measure and compare the actual bus frequency of SPI with this data.

Regards

Shankari G

KENGO AKIKAWA,

Hmm, Good to hear.

Great going !

Glad that it is resolved.

Regards

Shankari G