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About DDR_MDIV1 bit on AM389x/C6A816x/DM816x.

RY9983
Guru 10570 points

Hello,

I have a question about DDR PLL of AM389x/C6A816x/DM816x.
In evm816x.gel, DDR_MDIV1 is set as 0x4.
But, Flying adder synthesizer 1 does not exist on TRM(SPRUgx8 : P204 Figure1-71 DDR PLL Structure).

Could you let me know..
 - Do I need set up DDR_MDIV1?
if yes,
 - Where does DDR_MDIV1 be set on DDR PLL structure? (How can I determine this value?)

Best regards,
RY

  • 0
    TI__Expert 4245 points

    Hi,

    Since your query is very specific to the TRM, I'm moving your query to the DM816x/C6A816X/AM389x processor forum, so that other hardware experts maybe able to help.

  • 0 in reply to Siddharth Heroor
    Guru 10570 points

    Hello,
    Will you advise me someone?
    Please help!!

    RY

  • 0 in reply to RY9983
    Intellectual 650 points

    I have the same question as the original poster.  

    the DM8168 TRM says in section 1.16.1.2.17  "The DDRPLL_DIV1 register is used to control the DDR PLL Clock 1 post-divider frequency of the DDR clock. The default DIV1 value is 1" and the DDR1_MDIV field can be between 0-255.

    In the TRM figure 1-71 shows a fixed /2 and doesn't really show a DDR PLL Clock 1.

    Based on the text and the values used in u-boot I assume figure 1-71 is incorrect.

     I note that the values used in the u-boot tree for DDR_MDIV1 are 

    400 MHz 0x4

    531 MHz 0x3

    >= 648 MHz 0x2

  • 0 in reply to Andrew Dyer
    TI__Guru**** 170625 points

    Hi Andrew,

    Andrew Dyer said:
    Based on the text and the values used in u-boot I assume figure 1-71 is incorrect.

    Yes, I also suspect that this figure 1-71 is not fully correct, we should have DDR PLL clock 1. This clock signals is marked as ddr_pll_clk1_ck in the linux kernel source code, see file <kernel_installation>/arch/arm/mach-omap2/clock816x_data.c. This ddr_pll_clk1_ck has (by default) the frequency of 796.5 MHz, which value match with the u-boot and GEL file DDR PLL settings.

    BR,

    Pavel