J784S4 EVM-MDIO timing single is wired

Sai Wang

Intellectual 481 points

Part Number: TDA4VH-Q1

Tool/software:

Dear Hardware expert:

I am testing J784S4's mdio timing. found that its MDIO(AE37 AC36) 's signal is wired.

Note: green line is MDIO The yelow line is MDC

My question:

1、Why MDC‘s +width is not equal -width

2、 Why MDIO's some bit's rise time slow , and its fall line is just as MDC's rise line??

Is there a error here? How can i optimize here?

10 months ago

0 Doredla Sudheer Kumar 10 months ago

TI__Guru 63490 points

Hi,

Can you please check your Schematic whether MDC & MDIO are traversed in parallel like differential signals or not.

Please refer please refer to TI EVMs Schematics from "">www.ti.com/.../J784S4XEVM"

https://www.ti.com/lit/zip/sprr458

Best Regards,
Sudheer

0 ShreyasRao 10 months ago

TI__Guru 61870 points

Sai Wang,

I think that the yellow line is the MDC and green line is MDIO. The MDIO is open drain with a pullup resistor during the normal operation. That explains the slower rise time vs fast fall time. I am unsure why some bit have slower rise time vs other bits. I will check on this and get back.

0 Sai Wang 10 months ago in reply to Doredla Sudheer Kumar

Intellectual 481 points

Hi. the picture that i post is the J784S4 EVM's actual signal

0 ShreyasRao 10 months ago in reply to Sai Wang

TI__Guru 61870 points

How is the MDC generated? HW creates the MDC off the internal clock and the SW produces the MDC pulses based on the function called which can create variable Hi/Lo pulses.

Processors

Processors forum

J784S4 EVM-MDIO timing single is wired