6472 NOR flash boot

The C6472 does not have an EMIF controller internal to the part and does not support a direct boot from either NAND or NOR.   The NAND boot that you are referring to is accomplished using an I2C master boot and external FPGA connected to the C6472 with GPIOs.  You could use the same methodology and connect a NOR flash to the FPGA as opposed to the NAND flash but TI doesn't have an example of the FPGA programming or the programming of the NOR Flash.

of course. I know all you`ve mentioned above. I`m new to DSP programming and FLASH, where do I start in order to built a NOR DSP peripherial using FPGA?

The NAND interface was developed by Einfochips for the C6472 EVM.  They have the FPGA code for that interface on their website.  You can use that as a starting point but converting that to a NOR interface may be difficult and will result in a very slow boot.  The NAND flash was ideal for this application because it only uses 13bits for the entire interface (8bits data and 5 command bits).  Those bits can be generated using the 16bits of GPIO available on the C6472.  A typical 8bit NOR flash will have 8bits of data, up to 20bits of address and 3bits of command.  You will need to set up a set of registers in the FPGA and write those register to initiate a transfer using multiple accesses across the GPIO interface.  If you formatted you GPIO as an 8bit data interface with a few control lines, an 8bit memory read from your NOR flash would require a set of steps similar to the following.

1) Write the lower 8bits of address to the address[7:0] register in the FPGA

2) Write the middle 8bits of address to the address[15:8] register in the FPGA

3) Write the upper 8bits of address to the address[23:16] register in the FPGA

4) Write the read command to the status register in the FPGA. This will start the state machine in the FPGA to actually read the data from the NOR flash.

5) Check the status bit in the status register to see if the read is complete.  This bit will be set by the state machine when the read is complete and the data is available in the data register in the FPGA.

6) Once the status bit is set then read the data from the data register in the FPGA.

Obviously this is a big change to both the DSP code and the FPGA programming.  Example for this type of interface don't exist for either the DSP or the FPGA.