TMS320C6745 clock structure

richard seifert said:

1. As part of the PLL0 structure, SYSCLK7 is listed as the RMII clock to the EMAC.  There is also an I/O signal, RMII_MHZ_50_CLK that I think would be an input in this case.  What is the relationship between SYSCLK7 and RMII_MHZ_50_CLK?

This is discussed in the TRM Section 6.3.4 "EMAC Clocking".

richard seifert said:

Table 6-38 lists the typical period as 50ns.  Why was only a typical parameter specified?

This note follows the table:

"Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less."

richard seifert said:

2. Also, there is an MDIO_CLK that is an output.  It looks SYSCLK4 is the source of this clock.  Table 6-41 of the datasheet defines the maximum frequency as 2.5MHZ.  I am confused because SYSCLK4 is a fixed divide by 4.  Assuming that SYSCLK1 is 300MHZ, this would yield 75MHZ.  What am I missing here?

You are missing the CLKDIV field of the MDIO Control Register.  This gives you a 16-bit divider to get MDIO_CLK <= 2.5 MHz.

richard seifert said:

3. I am looking at using the 456MHZ version of the part.  I don’t see how I can configure the PLL to give me the 456MHZ SYSCLK1 and also give me all of the other clock frequencies needed to support the other interfaces, 50MHZ for EMAC, 133MHZ for EMIFB, 100MHZ for EMIFA.  Is there an example on how to do this.

For EMAC you need to supply RMII_MHZ_50_CLK separately.  There's a note in Section 6.2.4 "EMAC Clocking" that specifically says that SYSCLK7 will not meet the clock reference spec.  For EMIFB you can do 456MHz/4=114MHz.  For EMIFA you can do 456MHz/5=91.2MHz.  FYI, SYSCLK3 and SYSCLK5 do not require a fixed ratio to the CPU clock as documented in Table 6-2 "System Clock Domains" of the TRM.