[FAQ] AM62A3-Q1: AM62A3-Q1 PDN Power SI SIMULATION Questions

yin wenqing

Prodigy 30 points

Part Number: AM62A3-Q1

Tool/software:

Hello，I have some doubts about PDN simulation (Power SI), please help to solve it

1、Do I need to separate VDD_CORE-1 to 17 for simulation, or use VDD_CORE as a Port?

2、Do I need to include the PMIC FB loop in the simulation?

3、 Is the simulation starting frequency from 1Hz or from a minimum of 100kHz for the capacitor S2P?

2 months ago

0 Kallikuppa Sreenivasa 2 months ago

TI__Guru**** 157799 points

Hello yin wenqing

Thank you for the query.

Let me check with the team internally and update you.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 157799 points

Hello yin wenqing

Please refer below inputs i received:

Please note these are only recommendations and they need to contact their EDA vendor on what works best for their specific simulation environment.
1、Do I need to separate VDD_CORE-1 to 17 for simulation, or use VDD_CORE as a Port?
TI>> You can lump all VDD_CORE BGAs together as a single terminal for the port
2、Do I need to include the PMIC FB loop in the simulation?
TI>> If you are simulating only for AC impedance (target impedance checks) this is not required. The board layout from the inductor onwards (inductor not included) can be modeled and PMIC FB loop can be studied separately.
3、 Is the simulation starting frequency from 1Hz or from a minimum of 100kHz for the capacitor S2P?
TI>> There should be some DC frequency points added. Please check with your EDA vendor on the exact setup and simulation points needed to generate causal models.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 26 days ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 157799 points

Hi All,

I added additional inputs related to PDN and decoupling capacitors for reference.

The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth

PCB design & Dcap scheme combine to form your board's Power Distribution Network (PDN) that should meet recommended SoC PI performance targets for robust processor operations. Each PCB design has a "unique finger-print" based upon component placements, power & Gnd routing, layer assignments, via qtys & locations, Dcap mounting & loop inductance, Dcap parameters, etc. As a result, an optimized Dcap scheme will vary from one PCB design to another but should provide a system PDN that meets PI performance targets when combined together. Similarly, the PI simulation tools can impact the estimated ZvsF response values, especially above 3.0MHz where non-3D extraction tools can return better Z values (10-15% less than more accurate 3D tools). This ican be due to a non-3D tool is only extracting a PCB's X & Y design elements & assuming a power & Gnd via inductances. Due to the 3D nature of current flow across & through a PCB from power & Gnd planes on different PCB layers, a 3D extraction gives a more accurate series inductance estimate needed to more accurately model power & Gnd vias which leads to a more accurate power rail impedance (ZvsF) response

it would be difficult to comment on reducing the amount of decoupling caps without going through the exercise ourselves. That said, you can likely prioritize the high-current and sensitive analog rails, then look to share bypass caps when you hit space constraints. Having decap as close to the BGA as possible will reduce inductance and improve their efficacy (two supply vias with a shared decap would be better than a decap located far away in most circumstances).

Please be aware that each PCB design is unique and may need different Dcap scheme to meet recommended PI parameter targets

Regarding decoupling capacitors, the recommendation is to start with the EVMs decoupling and then optimize (if needed) based on your power simulation results.

For the placement of the Caps and values, we would still recommend using the EVM as a reference along with the PDN document.

SK uses an EMI Filter at 1uF, can I replace it with a general ceramic capacitor?

The SK performance has been tested with 3-T terminal caps.

You may have to add multiple 2-T caps for each cap and perform simulations to finalize the values.

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PDN application note

https://www.ti.com/lit/an/sprac76g/sprac76g.pdf

Regards,

Sreenivasa