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Interfacing Sitara AM3505/17 to an FPGA using the GPMC Interface

Gary Cochran
Intellectual 295 points
Other Parts Discussed in Thread: AM3505

We want to to interface Sitara to an FPGA via the GPMC. Timing diagrams in the the AM3505/17 TRM are unclear.  Unsure about  the following:

 a. can we setup a synchronous transfer ? or does it need to be async  transfer ? 
 b. Can we use multiplexed memory address ? See datasheet, section 6.4. 10-bits address ? 26-bits address ?
 c. What is the default mode register setting for the GPMC ? gpmc_clk freq ?
 d. Is it okay to have NAND flash and FPGA on GPMC bus, seperate chip selects, but each using a different operating/access mode ?
 e. What is read-to-write, write-to-read, back-to-back read/write, bus turn around cycle timing ? Would be preferable to have a timing diagram for this.

  • 0
    TI__Genius 9190 points

    Hello Gary,

    Gary Cochran said:

    We want to to interface Sitara to an FPGA via the GPMC. Timing diagrams in the the AM3505/17 TRM are unclear.  Unsure about  the following:

     a. can we setup a synchronous transfer ? or does it need to be async  transfer ? 
     b. Can we use multiplexed memory address ? See datasheet, section 6.4. 10-bits address ? 26-bits address ?
     c. What is the default mode register setting for the GPMC ? gpmc_clk freq ?
     d. Is it okay to have NAND flash and FPGA on GPMC bus, seperate chip selects, but each using a different operating/access mode ?
     e. What is read-to-write, write-to-read, back-to-back read/write, bus turn around cycle timing ? Would be preferable to have a timing diagram for this.

    a. Yes, you can configure for Sync or Async transfers.  This is controlled in the GPMC_CONFIG1_i register using the WRITETYPE and READTYPE bit fields please see section 9.1.7.2.10 of the TRM

    b. yes, multiplexed mode is available this is also controlled in the GPMC_CONFIG1_i register see bitfield MUXADDDATA.  You can also find info on this in table 9-2 of the TRM as well as section 9.1.3.3.

    c. do you mean after reset, or for a particular build of our code?  the default settings after a reset are also listed in the register info from the TRM in section 9.1.7.1 for the mode the config1 register is most likely what you are looking for.  typically the GPMC clock is set to 1/2 the L3 clock or 83MHz. 

    d. yes, you can have NAND on one CS and an FPGA on another.  You can configure each CS independently with different modes.

  • 0 in reply to Jeff Culverhouse
    Intellectual 805 points

    Hello Jeff, hello everybody.

    We intend to multiplex the  Sitara bus to control a display (all color lines) and SRAM 1 MB memory. As Jeff told, it is possible do it using chip selects.

    1- That chip select are configured in internal registers of Sitara or it is necessary a driver to control/synchronize the bus access?

    2- We can use the /CS to drive external muxes?

    3- That signals are asserted early enough to guarantee the correct data transfer?

  • 0 in reply to daniel formolo
    Guru 31670 points

    Daniel,

    I'm not really sure about your interface. But if you configure each chip select properly to appropriate address spaces, by just accessing the mapped address, chip selects will toggle automatically. So,

    1. You don't need a dedicated driver to toggling CS. You can achieve this by just doing a memory access of the corresponding address space.

    2. Yes, possible.

    3. Yes.