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AM6442: Where are ADC0-related CTRLMMR_PADCONFIG registers specified in TRM?

Guillaume Gonnet
Prodigy 20 points
Part Number: AM6442

Tool/software:

Hi support team,

For a project, I need to configure ADC0 inputs (the AINx pins) as General Purpose Inputs (GPI).
In the document AM64x/AM243x Technical Reference Manual (Rev. H), it is written in note (6) page 6478 that "Registers from CTRLMMR_PADCONFIG172[5-4] VGPIO_SEL to CTRLMMR_PADCONFIG179[5-4] VGPIO_SEL are for configuration ADC0_AIN[0-7] inputs". But these registers are not described anywhere in the TRM. 
In the section describing CTRLMMR_PADCONFIGx registers (or PADCFG_CTRL0_CFG0_PADCONFIGx as they are now named), table 5-14 only goes to 171, as if the CTRLMMR_PADCONFIG172..179 registers don't exist. Also, the VGPIO_SEL bits are not described in table 5-13, therefore I don't know what they are for.

Best regards,
Guillaume

  • +1
    TI__Mastermind 48608 points

    Hello Guillaume,

    Thanks for reaching out to Texas Instruments E2E support forum.

    Guillaume Gonnet said:
    therefore I don't know what they are for.

    You can consider those registers to be similar as other PADCFG registers. Those PADCONFIG registers are not used for GPI function on ADC and is removed from TRM.

    Guillaume Gonnet said:
    For a project, I need to configure ADC0 inputs (the AINx pins) as General Purpose Inputs (GPI).

    To achieve the above use case, please refer section 12.1.1.4.2.2 ADC GPI Integration of the TRM.

    Please refer below image.

    Regards,

    Tushar