TDA4AEN-Q1: Display Jittering problem on R5F

Hi,

Most likely, this is coming due to qos not being set for the TDA4AEN device. can we do some experiments to enable QoS and priority for DSS and see if it helps? 

Regards,

Brijesh

Hi, Brijesh.

Sure. Are you going to do those experiments on your side? or If you want me to do something, Just let me know how to test them.

Kind regards

Yongsig

Hi Yongsig,

I guess you are using SPL boot flow, so i want to take some qos changes from J721S2 to J722S and see if it helps in this case. I will share the patch by tomorrow for you to try out. 

Regards.

Brijesh

Hi Brijesh

I'm wondering if there will be an update.

Kind regards

Yongsig

Hi Yongsig,

Not yet, i am still checking it out. 

Regards,

Brijesh

Hi Yongsig,

can you please do one experiment? Once the Linux comes up, can you please write below registers using devmem utility and then run the usecase? Lets see if this resolves the artifact issue on DSS? 

devmem2 0x45D25100 w 0x80
devmem2 0x45D25104 w 0x80
devmem2 0x45D25108 w 0x80
devmem2 0x45D2510C w 0x80

devmem2 0x45D25000 w 0x76543210
devmem2 0x45D25004 w 0xfedcba98

Regards,

Brijesh

Hi Brijesh

I did as follows.

root@j722s-evm:~# devmem2 0x45D25100 w 0x80
/dev/mem opened.
Memory mapped at address 0xffff85882000.
Read at address  0x45D25100 (0xffff85882100): 0x00000000
Write at address 0x45D25100 (0xffff85882100): 0x00000080, readback 0x00000080
root@j722s-evm:~#
root@j722s-evm:~# devmem2 0x45D25104 w 0x80
/dev/mem opened.
Memory mapped at address 0xffffa9294000.
Read at address  0x45D25104 (0xffffa9294104): 0x00000000
Write at address 0x45D25104 (0xffffa9294104): 0x00000080, readback 0x00000080
root@j722s-evm:~#
root@j722s-evm:~# devmem2 0x45D25108 w 0x80
/dev/mem opened.
Memory mapped at address 0xffffb46fc000.
Read at address  0x45D25108 (0xffffb46fc108): 0x00000000
Write at address 0x45D25108 (0xffffb46fc108): 0x00000080, readback 0x00000080
root@j722s-evm:~#
root@j722s-evm:~# devmem2 0x45D2510C w 0x80
/dev/mem opened.
Memory mapped at address 0xffffafb4b000.
Read at address  0x45D2510C (0xffffafb4b10c): 0x00000000
Write at address 0x45D2510C (0xffffafb4b10c): 0x00000080, readback 0x00000080
root@j722s-evm:~#
root@j722s-evm:~# devmem2 0x45D25000 w 0x76543210
/dev/mem opened.
Memory mapped at address 0xffff82357000.
Read at address  0x45D25000 (0xffff82357000): 0x00000000
Write at address 0x45D25000 (0xffff82357000): 0x76543210, readback 0x76543210
root@j722s-evm:~#
root@j722s-evm:~# devmem2 0x45D25004 w 0xfedcba98
/dev/mem opened.
Memory mapped at address 0xffffb4d27000.
Read at address  0x45D25004 (0xffffb4d27004): 0x00000000
Write at address 0x45D25004 (0xffffb4d27004): 0xFEDCBA98, readback 0xFEDCBA98

But the artifact issue is still observed.

Best regards

Yongsig

ok, one more experiment, can you please try increasing value of busOrderId to 12 in Csirx_chCfgInit in source\drivers\csirx\v1\csirx.h file? Please note this will require building PDK drivers. Also please keep the above changes ie register settings. Lets see with both of these changes, if the issue goes away.

Regards,

Brijesh

Hi Brijesh.

I'm trying to migrate to PSDK 10.0.0.5 as of now.

I'll test on PSDK 10.0.0.5 with in a couple of days, and then I'll let you know the result.

Best regards

Yongsig

Thanks Yongsig.

HI Brijesh

Brijesh Jadav said:

can you please try increasing value of busOrderId to 12 in Csirx_chCfgInit in source\drivers\csirx\v1\csirx.h file? Please note this will require building PDK drivers

--> I did 'make sdk_clean' and 'make sdk_scrub' before re-build.

And then set the registers as above.

But this issue is not resolved even though migrated to PSDK 10.0.0.5.

Do you have another idea?

Best regards

Yongsig

Hi Yongsig,

Moving to SDK10.0 will not help, as even in SDK10.0, QoS registers are not setup. 

Let me check with the team to figure out if there is any more changes required. 

Regards,

Brijesh

Hi Yongsig,

Can you please apply attached changes on uboot, rebuild uboot and try it on J722S? This patch properly adds QoS support for DSS and is going to be available in next SDK.

/cfs-file/__key/communityserver-discussions-components-files/791/arm_2D00_mach_2D00_k3_2D00_j722s_2D00_add_2D00_QoS_2D00_Support_2D00_For_2D00_DSS.patch

Regards,

Brijesh

HI Brijesh

Thanks for your suggestion.

But, I can't apply that patch.

I attached my ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08\board-support\ti-u-boot-2024.04+git\arch\arm\mach-k3j722s_init.c.

// SPDX-License-Identifier: GPL-2.0
/*
 * J722S: SoC specific initialization
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include "sysfw-loader.h"
#include "common.h"
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>

struct fwl_data cbass_main_fwls[] = {
	{ "FSS_DAT_REG3", 7, 8 },
};

/*
 * This uninitialized global variable would normal end up in the .bss section,
 * but the .bss is cleared between writing and reading this variable, so move
 * it to the .data section.
 */
u32 bootindex __section(".data");
static struct rom_extended_boot_data bootdata __section(".data");

static void store_boot_info_from_rom(void)
{
	bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
	memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
	       sizeof(struct rom_extended_boot_data));
}

static void ctrl_mmr_unlock(void)
{
	/* Unlock all WKUP_CTRL_MMR0 module registers */
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
	mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);

	/* Unlock all CTRL_MMR0 module registers */
	mmr_unlock(CTRL_MMR0_BASE, 0);
	mmr_unlock(CTRL_MMR0_BASE, 1);
	mmr_unlock(CTRL_MMR0_BASE, 2);
	mmr_unlock(CTRL_MMR0_BASE, 4);
	mmr_unlock(CTRL_MMR0_BASE, 5);
	mmr_unlock(CTRL_MMR0_BASE, 6);

	/* Unlock all MCU_CTRL_MMR0 module registers */
	mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
	mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
	mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
	mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
	mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
	mmr_unlock(MCU_CTRL_MMR0_BASE, 6);

	/* Unlock PADCFG_CTRL_MMR padconf registers */
	mmr_unlock(PADCFG_MMR0_BASE, 1);
	mmr_unlock(PADCFG_MMR1_BASE, 1);
}

void board_init_f(ulong dummy)
{
	struct udevice *dev;
	int ret;

	if (IS_ENABLED(CONFIG_CPU_V7R))
		setup_k3_mpu_regions();

	/*
	 * Cannot delay this further as there is a chance that
	 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
	 */
	store_boot_info_from_rom();

	ctrl_mmr_unlock();

	/* Init DM early */
	ret = spl_early_init();
	if (ret)
		panic("spl_early_init() failed: %d\n", ret);

	/*
	 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
	 * regardless of the result of pinctrl. Do this without probing the
	 * device, but instead by searching the device that would request the
	 * given sequence number if probed. The UART will be used by the DM
	 * firmware image for various purposes and TIFS depends on us to
	 * initialize its pin settings.
	 */
	ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
	if (!ret)
		pinctrl_select_state(dev, "default");

	if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) {
		/*
		 * Allow establishing an early console as required for example
		 * when doing a UART-based boot. Note that this console may not
		 * "survive" through a SYSFW PM-init step and will need a re-init
		 * in some way due to changing module clock frequencies.
		 */
		ret = early_console_init();
		if (ret)
			panic("early_console_init() failed: %d\n", ret);
	}

	if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
		/*
		 * Configure and start up system controller firmware. Provide
		 * the U-Boot console init function to the SYSFW post-PM
		 * configuration callback hook, effectively switching on (or
		 * over) the console output.
		 */
		ret = is_rom_loaded_sysfw(&bootdata);
		if (!ret)
			panic("ROM has not loaded TIFS firmware\n");

		k3_sysfw_loader(true, NULL, NULL);
	}

	/*
	 * Force probe of clk_k3 driver here to ensure basic default clock
	 * configuration is always done.
	 */
	if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
		ret = uclass_get_device_by_driver(UCLASS_CLK,
						  DM_DRIVER_GET(ti_clk),
						  &dev);
		if (ret)
			printf("Failed to initialize clk-k3!\n");
	}

	preloader_console_init();

	/* Output System Firmware version info */
	k3_sysfw_print_ver();

	if (IS_ENABLED(CONFIG_CPU_V7R)) {
		/* Disable ROM configured firewalls right after loading sysfw */
		remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls));
	}

	if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) {
		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
		if (ret)
			panic("DRAM init failed: %d\n", ret);
	}

	debug("j722s_init: %s done\n", __func__);
}

static u32 __get_backup_bootmedia(u32 devstat)
{
	u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
				MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
	u32 bkup_bootmode_cfg =
			(devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
				MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;

	switch (bkup_bootmode) {
	case BACKUP_BOOT_DEVICE_UART:
		return BOOT_DEVICE_UART;

	case BACKUP_BOOT_DEVICE_USB:
		return BOOT_DEVICE_USB;

	case BACKUP_BOOT_DEVICE_ETHERNET:
		return BOOT_DEVICE_ETHERNET;

	case BACKUP_BOOT_DEVICE_MMC:
		if (bkup_bootmode_cfg)
			return BOOT_DEVICE_MMC2;
		return BOOT_DEVICE_MMC1;

	case BACKUP_BOOT_DEVICE_SPI:
		return BOOT_DEVICE_SPI;

	case BACKUP_BOOT_DEVICE_I2C:
		return BOOT_DEVICE_I2C;

	case BACKUP_BOOT_DEVICE_DFU:
		if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
			return BOOT_DEVICE_USB;
		return BOOT_DEVICE_DFU;
	};

	return BOOT_DEVICE_RAM;
}

static u32 __get_primary_bootmedia(u32 devstat)
{
	u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
				MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
	u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
				MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;

	switch (bootmode) {
	case BOOT_DEVICE_OSPI:
		fallthrough;
	case BOOT_DEVICE_QSPI:
		fallthrough;
	case BOOT_DEVICE_XSPI:
		fallthrough;
	case BOOT_DEVICE_FAST_XSPI:
		fallthrough;
	case BOOT_DEVICE_SPI:
		return BOOT_DEVICE_SPI;

	case BOOT_DEVICE_ETHERNET_RGMII:
		fallthrough;
	case BOOT_DEVICE_ETHERNET_RMII:
		return BOOT_DEVICE_ETHERNET;

	case BOOT_DEVICE_EMMC:
		return BOOT_DEVICE_MMC1;

	case BOOT_DEVICE_SPI_NAND:
		return BOOT_DEVICE_SPINAND;

	case BOOT_DEVICE_MMC:
		if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
				MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
			return BOOT_DEVICE_MMC2;
		return BOOT_DEVICE_MMC1;

	case BOOT_DEVICE_DFU:
		if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
		    MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
			return BOOT_DEVICE_USB;
		return BOOT_DEVICE_DFU;

	case BOOT_DEVICE_NOBOOT:
		return BOOT_DEVICE_RAM;
	}

	return bootmode;
}

u32 spl_boot_device(void)
{
	u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
	u32 bootmedia;

	if (bootindex == K3_PRIMARY_BOOTMODE)
		bootmedia = __get_primary_bootmedia(devstat);
	else
		bootmedia = __get_backup_bootmedia(devstat);

	debug("j722s_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
	      __func__, devstat, bootmedia, bootindex);
	return bootmedia;
}

u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
	u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
	u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
				MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
	u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
			    MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;

	switch (bootmode) {
	case BOOT_DEVICE_EMMC:
		return MMCSD_MODE_EMMCBOOT;
	case BOOT_DEVICE_MMC:
		if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
			return MMCSD_MODE_RAW;
	default:
		return MMCSD_MODE_FS;
	}
}

It seems like you use another version.

Best regards

Yongsig

Hi Yongsig,

For SDK10.0, can you please apply attached patch on uboot, rebuild uboot and check with the new uboot?

/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_Added_2D00_support_2D00_for_2D00_Setting_2D00_QoS_2D00_for_2D00_DSS.patch

Regards,

Brijesh

Hi Brijesh

Unfortunately, the Jittering issue is still observed.

Please review the process I did:

1. apply the patch
2. make u_boot_clean
3. make u_boot
4. staging the files

   usami@usami-HP-ZBook-Fury-15-6-inch-G8-Mobile-Workstation-PC:~/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08$ make u-boot-a53_stage
   mkdir -p /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/built-images
   cp /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/ti-u-boot-2024.04+git/build/a53/tispl.bin /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/built-images/tispl.bin
   cp /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/ti-u-boot-2024.04+git/build/a53/u-boot.img /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/built-images/u-boot.img
   usami@usami-HP-ZBook-Fury-15-6-inch-G8-Mobile-Workstation-PC:~/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08$ make u-boot-r5_stage
   mkdir -p /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/built-images
   cp /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/ti-u-boot-2024.04+git/build/r5/tiboot3-j722s-hs-fs-evm.bin /home/usami/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/built-images/tiboot3.bin

5. copy built-images/* to BOOT section of the sdcard

   ongsigvb22@yongsigvb22:~/usami_labtop/workspace/ti_psdk/100_j722s/default/ti-processor-sdk-linux-adas-j722s-evm-10_00_00_08/board-support/built-images$ cp -rvf * /media/yongsigvb22/BOOT/
   'tiboot3.bin' -> '/media/yongsigvb22/BOOT/tiboot3.bin'
   'tispl.bin' -> '/media/yongsigvb22/BOOT/tispl.bin'
   'u-boot.img' -> '/media/yongsigvb22/BOOT/u-boot.img'
   

--> NOT RESOLVED 

 Additionally, I tried to set the registers:

         6. 

root@j722s-evm:~# devmem2 0x45D25100 w 0x80
/dev/mem opened.
Memory mapped at address 0xffff8c813000.
Read at address  0x45D25100 (0xffff8c813100): 0x00000000
Write at address 0x45D25100 (0xffff8c813100): 0x00000080, readback 0x00000080
root@j722s-evm:~# devmem2 0x45D25104 w 0x80
/dev/mem opened.
Memory mapped at address 0xffff9cd7b000.
Read at address  0x45D25104 (0xffff9cd7b104): 0x00000000
Write at address 0x45D25104 (0xffff9cd7b104): 0x00000080, readback 0x00000080
root@j722s-evm:~# devmem2 0x45D25108 w 0x80
/dev/mem opened.
Memory mapped at address 0xffffa04e9000.
Read at address  0x45D25108 (0xffffa04e9108): 0x00000000
Write at address 0x45D25108 (0xffffa04e9108): 0x00000080, readback 0x00000080
root@j722s-evm:~# devmem2 0x45D2510C w 0x80
/dev/mem opened.
Memory mapped at address 0xffffa1ffa000.
Read at address  0x45D2510C (0xffffa1ffa10c): 0x00000000
Write at address 0x45D2510C (0xffffa1ffa10c): 0x00000080, readback 0x00000080
root@j722s-evm:~# devmem2 0x45D25000 w 0x76543210
/dev/mem opened.
Memory mapped at address 0xffffbc1ce000.
Read at address  0x45D25000 (0xffffbc1ce000): 0x00000000
Write at address 0x45D25000 (0xffffbc1ce000): 0x76543210, readback 0x76543210
root@j722s-evm:~# devmem2 0x45D25004 w 0xfedcba98
/dev/mem opened.
Memory mapped at address 0xffffafe27000.
Read at address  0x45D25004 (0xffffafe27004): 0x00000000
Write at address 0x45D25004 (0xffffafe27004): 0xFEDCBA98, readback 0xFEDCBA98

--> NOT RESOLVED as well.

Best regards

Yongsig