AM62A7-Q1: Network PHY chip hardware test mode

Hi Yuwei,

Which SDK are you using for this? Linux or MCU+? This will help us assign to the correct team.

Thanks,

Anshu

Hi Anshu,

The SDK we are using is PROCESSOR-SDK-LINUX-AM62A 09.02.00.

Thanks,

Yuwei

Hi Yuwei,

I'll re-assign the thread. Please allow some time for a response.

Thanks,

Anshu

Hi Anshu,

Looking forward to your response.

Thanks,

Yuwei

Hi YuWei,

For the RGMII timing, the most important timing requirements that must be met are Tsetup and Thold for successful communication.

Tsetup and Thold times requirements are defined in section 6.6 Timing Requirments of the datasheet.

If Tsetup and Thold cannot be met through hardware design, there is an option to tune the RGMII delay to meet Tsetup and Thold in DP83TC812 register 0x602.

Best regards,

Melissa

Can you help provide the parameters of Tskew (shift)?

Hi Liu,

Tskew(shift) will be a minimum of 2ns. There is no maximum. 

Best regards,

Melissa

Okay, thank you.If the hardware configuration is in align mode, can you help provide the software configuration or code?

HI Melissa Chang :please provide the parameters for Thold (shift) and Tsetup (shift)， I couldn't find them in the manual

Hi,

If the HW is strapped to Align mode, you can program shift mode by writing to register 0x602[1:0] as described in the datasheet. Toggling these bits will add a delay of 2ns.

For Tsetup and Thold in shift mode, the minimum requirement is 1ns for both.

Best regards,

Melissa

HI  Melissa Chang

Can you help explain how Thold (shift) tests waveforms? According to the manual, it tests the change from CLK rising to TX-EN，As shown in the figure below, which part should we test for Thold (shift) time

Hi,

Can you provide a scope shot of the one of the data lines (TXD[3:0]), TX_CLK, and TX_CTRL?

Could you also label which waveforms are which?

Best regards,

Melissa

HI Melissa Chang:As shown in the figure below,Yellew is TCLK,Red is CTRL,Blue is TXD0,which part should we test for Thold (shift) time

Hi,

Thanks for pointing this out, I did not see the legend at the bottom intially.

In your photo, the Setup time is betwen red and blue lines. This is the time for the CLK to transition high after data has changed.

Hold time is the blue and purple lines. This is the time that the data is stays the same while CLK is HIGH. 

Best regards,

Melissa

Thank you for your reply. Could you please help confirm again this is the set up and hold time in (shift) mode? This is different from the timing diagram given in the TI manual.

Okay, thank you for your reply. There is no problem with RGMII communication, it's just that the testing method in the manual is not understood and there is no shift mode parameter, so I want to confirm with you