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6455 EMIF Write-Read Ordering

Michael Courtney
Prodigy 150 points


In the EMIF User's Guide (SPRU971E), it discusses a possible race condition in section 7.3. It says that the EDMA3 controller will always wait for an EMIF write to complete before signaling an interrupt to the system, but that there are other masters that do not have a hardware guarantee of write-read ordering. It then refers you to the device-specific data manual for a list of masters that need the included software workaround. Looking through the C6455 data sheet (SPRS276I), it has the same statement that some masters need a software workaround, but does not contain a list of masters that need the workaround. Does this list exist someplace? And which masters in the C6455 require the SW workaround?

 

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    TI__Guru*** 125430 points

    The CPU is the master most likely to encounter this issue.  For example, if you were writing to a memory mapped register in an FPGA and then immediately afterward needed to read back a status register elsewhere in the FPGA (different 2048 byte block) then the read would get ahead of the write.

    The HPI/PCI would also behave in a similar manner.  In other words, if an external device was writing data into the 6455 through the HPI you would need to follow some of the steps listed in the HPI User Guide to ensure that the write FIFO is empty before you issue an interrupt to the processor.  Otherwise the CPU might try to read data that has not yet landed in memory.