J721EXSOMXEVM: Custom .xer5f firmware creation

Hello,

I didn't get You fully. You are expecting to create a custom example fro R5F core then you need to create a separate folder and write makefile for it which eventually get creates binary.

Regards

Tarun Mukesh 

Hi!

Thanks for the reply!

When the SoC boots into Arago Linux, only the A72 cores are available for running code. If I compile and run a benchmark like whetstone, then one of the A72 core will execute. Apart from the two A72, the J721 contains four R5F cores, which I also want to benchmark, possibly the same way.

I would prefer a way that would not require me to rebuilt the whole kernel image. Can this be done with RemoteProc?

software-dl.ti.com/.../UG-RemoteProc.html

If the kernel rebuilt is a must, is there a guide on how to modify the makefile?

Best regard,

Marton

Hello,

You no need to re build the whole kernel image, if you have the .xer5f executable to test the benchmark then you can just soft link it to respective core remote proc.

Regards

Tarun Mukesh

Hello!

I'm having some difficulties regarding the .xer5f resource file creation:

I'm using CCS v12.2 on my Win machine. I've created a CCS Project like that:


then added the dhry.h, dhry_1.c and dhry_2.c from here: https://github.com/sifive/benchmark-dhrystone/tree/master

The project won't build howver, since sys/times.h is missing:

Pretty straightforward error. So far I've tried to hack it with adding manually the times header from here: https://sites.uclouvain.be/SystInfo/usr/include/sys/times.h.html

Problem is this method leads to a loophole of different header includes. I would assume that this can be done by configuring the compiler in Eclipse, but I'm not too familiar with the Eclipse Preferences.

What am I messing up here?

BR,

Marton

Still facing the same issue of missing sys/times.h with the J721_EVM

There is a document of Cortex-R5F benchmark results:
https://www.ti.com/lit/an/spracv1b/spracv1b.pdf?ts=1730364092379&ref_url=https%253A%252F%252Fwww.google.com%252F

So it's must be possible. The question still holds:
- Do you have a dhrystone version that is tailored (thus does not use sys/times.h as a resource) to R5F timer?

- Is there an ARM toolchain for Cortex-R5F MCUs? Maybe this way I could build the resource files, since I have a Makefile.

Thanks,

Marton