Part Number: SK-AM64B
Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello TI team!
I have implemented an application to check memory read and memory write times.
It is very simple.
Read and write to a global variable.
Tested with MSRAM, SHARED MEMORY and DDR
Tested with cache memory and non-cache memory
The test cases are as follows
I would expect the non-cache RW test to take longer than the cache test.
However, the processing time was about the same.
It seems that the cache settings are wrong.
Q1. How do I set cache and non-cache settings?
I'm not sure about example.syscfg, so I'm using almost the same settings as in the IPC notify echo sample example.syscfg.
I changed the MPU “Region Attributes” setting for cache and non-cache settings.
Is the setting incorrect?
Q2: There is no MEMORY CONFIGURATOR in the example.syscfg of A53. How can I set the Memory Region, Section?
A53 does not have a MEMORY CONFIGURATOR.
R5F has a MEMORY CONFIGURATOR.
A53 example.syscfg
In the R5F hello world application, I added DDR to Memory Region and changed “Code and Read-Only Data” from MSRAM to DDR in Sction.
How do I get the A53 hello world application to work with DDR?
Q3: Can MSRAM and DDR be used together on the A53 core?
I have previously heard that MSRAM and DDR cannot be used together on the A53 core.
I have looked at the Technical Reference Manual, but I am not sure.
My goal is to develop an IPC notify echo application that works with DDR.
Can I place the R5F, A53, M4F program code in DDR and SHARED MEMORY in MSRAM as shown below?
How can I modify the example.syscfg for A53?
Regards,
Yoshiki
