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DRA821U: DRA821U: DRA821U: DRA821U: DRA821U: DRA821U: J721EXCPXEVM/ J7200XSOMXEVM/DRA821 - Ports/Balls on DRA821 Recommended for use by TI

Part Number: DRA821U
Other Parts Discussed in Thread: J7200XSOMXEVM, DRA821

Tool/software:

Hello,

We have ordered several of TI's 721EXCPXEVM/ J7200XSOMXEVM/DRA821 for evaluation and prototyping. What ports/balls does TI recommend customers use on the DRA821 for the 2 X 1Gbit SGMII and the PCIe X2?

For context, we require 2 SGMII ports that will take 2 of the 4 SERDES channels and we need 1 PCIe port that supports NVMe Gen 3 X2 (or 2 TX/RX Channels, or the last 2 SERDES  channels).
 "X2" is common way to designate if NVMe SSD has 2 channels to support one SSD, and X4 is common for most consumer SSDs --but we only have 2 channels remaining. 
 Therefore, what is TI's recommendation for balls/ports to assign to SGMII #1, SGMII #2 and NVMe SSD X2?  Thank you.
  • Sunny,

    For SGMII, you can use any of the 2 lanes on IP1, and then for the PCIe, you can use the other 2 lanes on IP2 configured as single link as multilink may not be supported with the single PCIe instance. The other thing to note here is that both SGMII and PCIe will use the 100MHz internal ref clk without SSC.

  • Thank you. We had planned to use an external 100MHz clock if you think that is still Ok. Can you elaborate on comment "without SSC"? We are not familiar with this term. What does the acronym stand for and what do you mean? Also, is there any section of the data sheet or other reference material for your information above so I can supply it  to the team? Thank you again.

  • SSC refers to Spread Spectrum clocking. For PCIe it is optional to use or not use SSC whereas SSC is not supported by the SGMII standard.

    Yes, You could also use the external 100MHz clock instead of the internal ref clk.