OMAP-L137 NOR "Peripheral Open Failed"

Justin Waters

Other Parts Discussed in Thread: OMAP-L137

I am working with a custom board based on the OMAP-L137 processor. We are having issues getting it to load a first stage bootloader from NOR flash. At power up, the DSP appears to execute the boot ROM code, and then fails to read it. Using the Debug GEL File from http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files, I can see that the Pin Strapping is indeed set for NOR, but I receive the error "Peripheral Open Failed".

Here's the interesting part- if I halt the DSP using a JTAG, then reset the board (or even simply set the PC back to the beginning of the boot ROM code), then let the board run, it will successfully load my AIS image from NOR flash and run properly. If I don't halt the DSP and simply reset, it fails in a similar manner as before. Also note that the behavior is the same if we do not use *any* GEL files. I've also tried to verify using Legacy NOR mode, but it doesn't seem like the boot ROM is capable of reading the configuration word from NOR.

The reset and NOR hardware is somewhat complex (due to the addressing limitations of the OMAP-L137, it uses D Flip Flops to latch higher order bits). At first glance, everything seems to be okay with that aspect of the board, although we do have hardware engineers checking out the design again just to be sure.

My question is, what are some things that could cause the "Peripheral Open Failed" error? Are there any additional mechanisms for debugging the boot ROM besides the Debug GEL file?

over 14 years ago

0 Daniel Allred over 14 years ago

TI__Genius 17355 points

If the boot pin settings indicate the NOR boot setting was latched, and you get a "Peripheral Open Failed" message, then that indicates that the config word was not read correctly. Is your NOR flash connected as 8-bit or 16-bit? Also can you report the ROM revision number (or the entire contents of the debug Gel output)? If possible, it would be useful to see traces of the bus activity that results in the failure. You should see at least two reads of the config word done by the ROM before the ROM aborts.

Note that all bits of the config word must be 0 if they are not part of one of the fields used in the config word.

Regards, Daniel

0 Justin Waters over 14 years ago in reply to Daniel Allred

Prodigy 20 points

Thank you for the response!

The NOR flash is 16-bit. We are using the configuration word 0x00000021 for the AIS image, 0x00000001 for legacy NOR. I've tried permutations of those as well, in case there was something odd with the way it was addressing the bytes. As I said before, it reads it properly after a reset occurs and the processor is halted, so I'm fairly confident in the format of the configuration word.

We are using revision 2.0, and one of the hardware guys found the errata about "Intermittent Boot Failures" on this revision. We are currently investigating this- it seems promising.

For what it's worth, the Boot ROM always ends up looping at the same addresses when it fails: 0x712144 0x712120 0x7120e0.

ROM info from the debug GEL (which has a divide by zero error in it, by the way):

Fullscreen 7455.debug.txt Download

---------------------------------------------
|             Device Information            |
---------------------------------------------
DEV_INFO_00 = 0x9B7DF02F
DEV_INFO_01 = 0x00000000
DEV_INFO_02 = 0x0000F371
DEV_INFO_03 = 0x00000022
DEV_INFO_04 = 0x00000000
DEV_INFO_05 = 0x000003E0
DEV_INFO_06 = 0x00000200
DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 8-0-152949-25-29-58
DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 0,0,0,15700
-----
DEV_INFO_17 = 0x00030003
DEV_INFO_18 = 0x00000000
DEV_INFO_19 = 00000
-----
DEV_INFO_20 = 0x30303864
DEV_INFO_21 = 0x3330306B
DEV_INFO_22 = 0x00000000
DEV_INFO_23 = 0x00000000
-----
DEV_INFO_24 = 0x1903A01D
DEV_INFO_25 = 0x08025575
DEV_INFO_06 = 0x00000200
DEV_INFO_26 = 0x7AA80000


---------------------------------------------
|               BOOTROM Info                |
---------------------------------------------
ROM ID: d800k003 
Silicon Revision 2.0
Boot pins: 62321
Boot Mode: NOR (0x0000F371)

ROM Status Code: 0x00000005 
Description: Peripheral Open Failed

Program Counter (PC) = 0x00712144

---------------------------------------------
|              Clock Information             |
---------------------------------------------

PLLs configured to utilize 1.2V square wave input.
ASYNC3 = PLL0_SYSCLK2

NOTE:  All clock frequencies in following PLL sections are based
off OSCIN = 25 MHz.  If that value does not match your hardware
you should change the #define in the top of the gel file, save it,
and then reload.

---------------------------------------------
|              PLL0 Information             |
---------------------------------------------

PLL0_SYSCLK1 = 300 MHz
PLL0_SYSCLK2 = 150 MHz
PLL0_SYSCLK3 = 100 MHz
PLL0_SYSCLK4 = 75 MHz
PLL0_SYSCLK5 = 50 MHz
PLL0_SYSCLK6 = 300 MHz
PLL0_SYSCLK7 = 50 MHz

---------------------------------------------
|              PSC0 Information             |
---------------------------------------------

State Decoder:
 0 = SwRstDisable (reset asserted, clock off)
 1 = SyncReset (reset assered, clock on)
 2 = Disable (reset de-asserted, clock off)
 3 = Enable (reset de-asserted, clock on)
>3 = Transition in progress

Module 0:	EDMA3CC (0)        STATE = 3
Module 1:	EDMA3 TC0          STATE = 3
Module 2:	EDMA3 TC1          STATE = 3
Module 3:	EMIFA (BR7)        STATE = 3
Module 4:	SPI 0              STATE = 3
Module 5:	MMC/SD 0           STATE = 3
Module 6:	AINTC              STATE = 3
Module 7:	ARM RAM/ROM        STATE = 3
Module 9:	UART 0             STATE = 3
Module 10:	SCR 0 (BR0/1/2/8)  STATE = 3
Module 11:	SCR 1 (BR4)        STATE = 3
Module 12:	SCR 2 (BR3/5/6)    STATE = 3
Module 13:	PRUSS              STATE = 3
Module 14:	ARM                STATE = 3
Module 15:	DSP                STATE = 3

---------------------------------------------
|              PSC1 Information             |
---------------------------------------------

State Decoder:
 0 = SwRstDisable (reset asserted, clock off)
 1 = SyncReset (reset assered, clock on)
 2 = Disable (reset de-asserted, clock off)
 3 = Enable (reset de-asserted, clock on)
>3 = Transition in progress

Module 1:	USB0 (2.0)         STATE = 3
Module 2:	USB1 (1.1)         STATE = 3
Module 3:	GPIO               STATE = 3
Module 4:	UHPI               STATE = 3
Module 5:	EMAC               STATE = 3
Module 6:	EMIFB (BR20)       STATE = 3
Module 7:	MCASP0 + FIFO      STATE = 3
Module 8:	MCASP1 + FIFO      STATE = 3
Module 9:	MCASP2 + FIFO      STATE = 3
Module 10:	SPI 1              STATE = 3
Module 11:	I2C 1              STATE = 3
Module 12:	UART 1             STATE = 3
Module 13:	UART 2             STATE = 3
Module 16:	LCDC               STATE = 3
Module 17:	eHRPWM (all)       STATE = 3
Module 20:	eCAP (all)         STATE = 3
Module 21:	eQEP 0/1           STATE = 3
Module 24:	SCR8 (Br15)        STATE = 3
Module 25:	SCR7 (Br12)        STATE = 3
Module 26:	SCR12 (Br18)       STATE = 3
Module 31:	L3 RAM (Br13)      STATE = 3

-Justin

Processors

Processors forum

OMAP-L137 NOR "Peripheral Open Failed"