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C6748 DSP no SPI1 interrupts?

I'm modifying a fairly mature DSP project which uses the SPI port (1) to communicate with another device, where the DSP is the master.  The current implementation polls the SPI peripheral for TX buffer empty, and RX buffer full, but I'd like to modify it to be interrupt driven.  I have read, and followed the information in sprufm4i.pdf for setting up the SPI interrupts.  I can verify the interrupts occuring properly in the SPIFLG, and the INTVEC1 registers.  According to this document the SPI peripheral should generate SPINT1 (interrupt). (Figure 1).  The system currently has several other interrupts mapped to the Interrupt Controller, for EVT1, including the HPI, and a GPIO interrupt which all seem to work properly.  In spruh77.pdf, Table 3-1, it lists SPI1_INT as event 43, one of the events that triggers the EVT1 interrupt as well.  I unmasked event 43 (I tried unmasking all the events except the timer), but it still won't hit my breakpoint in the Interrupt Service Routine.  (Breakpoint hit for HPI interrupt, and GPIO interrupt, so interrupts are enabled, not masked).  Is the SPINT1 signal described in sprufm4i.pdf the same signal as event 43 described in the Megamodule in spruh77.pdf?  Any idea why I can't seem to get the SPI1 interrupt to work?

I have successfully implemented a similar scheme with both McBsp and I2C on a 6482 DSP, and never had this much trouble before.

  • Did you program SPILVL to map the interrupts to INT1?  Have you tried using an interrupt directly rather than going through the combiner?  Some directions on how to go about this process using DSP/BIOS are discussed here:

    http://processors.wiki.ti.com/index.php/Setting_up_interrupts_in_DSP_BIOS

     

  • Yes, and yes.  I guess I thought that went without saying ;-)

     

    Just to clarify,

    SPIINT0 and SPILVL (sprufm4i) are both set to 0x35F - in an attempt to enable all the SPI interrupts.  (the appropriate ones do get set in SPIFLG, and INTVEC1)

    I tried mapping event 43 (SPI1_INT in spruh77) to INT[13] in the mega-module (sprufk5a), which had previously been unused.

    I also tried enabling the McBsp RX interrupt event 89 (MCBSP1_RINT) to EVT2, and it works just fine.  I have similar ISRs for EVT0, EVT1, EVT2, and EVT3.

    Just out of curiosity, I understand why there is a SPIDAT0, and SPIDAT1 - to tx data on the different SPI peripherals.  Why is there a SPIINT0 but no SPIINT1, and a INTVEC1 but no INTVEC0?  Is it possible to use both SPI peripherals, and have them both generate interrupts?  (I'm NOT trying to do that, only using SPI1).

     

  • I think I figured it out.  I tried masking the TX buffer empty interrupt (SPIINT0 = 0x15F).  As soon as the SPI is enabled, the TX buffer empty flag got set (because the buffer was empty), but this occurred at initialization, before interrupts were enabled.  I suspect since that interrupt was never serviced, we never got any more interrupts.  By masking the TX interrupt, I'm getting RX interrupts now, and I think I can make it work.

  • Sounds reasonable. Thanks for the follow-up reply.