This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: [DRA821U] Main CPSW RGMII issue

Part Number: TDA4VM
Other Parts Discussed in Thread: DRA821U, DRA821

Tool/software:

Dear TI

We made a new test board with J7200(DRA821U)

I connected PHY to CPSW5G port 1(RGMII1)

|  CPSW5G        port 1       | -- RGMII -- | TI PHY(DP83867)    |

And I also changed dts like below

	main_mdio0_pins_default: main_mdio0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0xa8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
			J721E_IOPAD(0xa4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
		>;
	};
	main_rgmii1_pins_default: main_rgmii1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AA17) RMII1_RXD0.RGMII1_RD0 */
			J721E_IOPAD(0x8, PIN_INPUT, 4) /* (Y15) RMII1_RXD1.RGMII1_RD1 */
			J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AA20) RMII1_CRS_DV.RGMII1_RD2 */
			J721E_IOPAD(0x10, PIN_INPUT, 4) /* (Y17) RMII1_RX_ER.RGMII1_RD3 */
			J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AA19) RMII1_TXD1.RGMII1_RXC */
			J721E_IOPAD(0x14, PIN_INPUT, 4) /* (Y16) RMII1_TXD0.RGMII1_RX_CTL */
			J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (Y18) MCAN2_TX.RGMII1_TD0 */
			J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (Y19) MCAN2_RX.RGMII1_TD1 */
			J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (Y21) MCAN3_TX.RGMII1_TD2 */
			J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (W16) MCAN3_RX.RGMII1_TD3 */
			J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (Y20) MCAN4_RX.RGMII1_TXC */
			J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (W15) MCAN4_TX.RGMII1_TX_CTL */
		>;
	};

&cpsw0 { 
	pinctrl-names = "default"; 
	pinctrl-0 = <&main_rgmii1_pins_default>; 

	status = "okay";
}; 

&cpsw5g_mdio { 

	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio0_pins_default>;
	
	#address-cells = <1>;
	#size-cells = <0>;
	
	main_phy0: ethernet-phy@0 { 
		reg = <0>; 
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 
		ti,min-output-impedance;
	};
}; 

&cpsw0_port1 { 
	status = "okay";
	
	phy-mode = "rgmii-rxid"; 
	phy-handle = <&main_phy0>;
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>; 
};

It generates kernel panic

   14.222084] NETDEV WATCHDOG: eth0 (am65-cpsw-nuss): transmit queue 0 timed out
[   14.229333] WARNING: CPU: 1 PID: 0 at net/sched/sch_generic.c:525 dev_watchdog+0x214/0x220
[   14.229359] Modules linked in: rpmsg_client_sample rpmsg_ctrl rpmsg_char virtio_rpmsg_bus rpmsg_ns ti_am335x_adc cdns3 kfifo_buf cdns_usb_common spidev crct10dif_ce phy_can_transceiver hbmc_am654 hyperbus_core ti_k3_r5_remoteproc k3_j72xx_bandgap ti_am335x_tscadc sa2ul pci_j721e_ep pcie_cadence_ep pci_j721e_host pcie_cadence_host pci_j721e cdns3_ti pcie_cadence rti_wdt spi_omap2_mcspi optee_rng rng_core cfg80211 rfkill fuse drm drm_panel_orientation_quirks ipv6
[   14.229456] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 6.1.80-gcfac743d18fc-dirty #28
[   14.229465] Hardware name: PKAA ACU board (DT)
[   14.229468] IRQ stage: Linux
[   14.229473] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   14.229482] pc : dev_watchdog+0x214/0x220
[   14.229490] lr : dev_watchdog+0x214/0x220
[   14.229497] sp : ffff80000afabb30
[   14.229500] x29: ffff80000afabb30 x28: 0000000000000005 x27: ffff800008a1e170
[   14.229513] x26: ffff80000ad27dc0 x25: ffff00087f7b7f68 x24: ffff80000afabc00
[   14.229524] x23: ffff80000ad27000 x22: 0000000000000000 x21: ffff000801b8239c
[   14.229535] x20: ffff000801b82000 x19: ffff000801b82448 x18: ffffffffffffffff
[   14.229545] x17: 6f2064656d697420 x16: 3020657565757120 x15: 74696d736e617274
[   14.229556] x14: 203a297373756e2d x13: ffff80000ad41870 x12: 00000000000005e8
[   14.229566] x11: 00000000000001f8 x10: ffff80000ad99870 x9 : 0000000000000400
[   14.229577] x8 : 0000000000000000 x7 : ffff0008085ba3e8 x6 : 000000004b1717a6
[   14.229587] x5 : 0000000000000003 x4 : ffff800874bf1000 x3 : ffff800874bf1000
[   14.229597] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0008000f6580
[   14.229608] Call trace:
[   14.229612]  dev_watchdog+0x214/0x220
[   14.229619]  call_timer_fn.constprop.0+0x24/0x80
[   14.229632]  __run_timers.part.0+0x1f0/0x234
[   14.229641]  run_timer_softirq+0x3c/0x7c
[   14.229650]  _stext+0x124/0x27c
[   14.229657]  __irq_exit_rcu+0xb4/0xe0
[   14.229666]  irq_exit+0x10/0x20
[   14.229673]  arch_do_IRQ_pipelined+0x48/0x70
[   14.229682]  sync_current_irq_stage+0x168/0x270
[   14.229696]  __inband_irq_enable+0x78/0x8c
[   14.229709]  inband_irq_enable+0x10/0x20
[   14.229714]  arch_cpu_idle+0x1c/0x2c
[   14.229722]  default_idle_call+0x50/0x6c
[   14.229735]  do_idle+0x23c/0x2b0
[   14.229747]  cpu_startup_entry+0x34/0x40
[   14.229758]  secondary_start_kernel+0x138/0x164
[   14.229769]  __secondary_switched+0xb0/0xb4
[   14.229777] ---[ end trace 0000000000000000 ]---

And it shows below kernel message continuosly.

am65-cpsw-nuss c000000.ethernet eth0: txq:0 DRV_XOFF:0 tmo:37812 dql_avail:-90 free_desc:515

Could you check and give some advice how to debug it ?

FYI, I'm using "ti-processor-sdk-linux-j7200-evm-09_02_00_04"

BR

Jace

  • Hi,

    May I know which boot flow you are using?

    Also, confirm that ETHFW is not loaded on MCU2_0?

    If you are using SBL Optimized boot flow, where u-boot is not present. Please refer to FAQ [How to resolve NETDEV WATCHDOG error in Linux in SBL optimized boot flow], and the follow the fix suggested there and confirm once.

    Best Regards,
    Sudheer

  • Hi Sudheer.

    I don't know the boot flow of our board.

    Our reference is J2700X SOM board and is using below boot binaries.

    - tiboot3.bin, tispl.bin, u-boot.img

    so it seems that I'm not using SLB Optimized boot flow since it uses u-boot.

    And I don't understand clearly, what is ETHFW and MCU2_0.

    Could you add some more information about them ?

    BR

    Jace

  • Hi,

    Our reference is J2700X SOM board and is using below boot binaries.

    - tiboot3.bin, tispl.bin, u-boot.img

    Can you please check your Linux terminal log, if you are observing u-boot prints then u-boot is present.

    And I don't understand clearly, what is ETHFW and MCU2_0.

    Default CPSW5G is enabled by ETHFW application running on MCU2_0. It will configure in QSGMII mode.
    Make sure that firmware binary loading on MCU2_0 is not ETHFW image, If ETHFW then softlink ipc echo test binary to MCU2_0 (main_r5f0_0).

    By default ETHFW binary might be soft linked to MCU2_0 image. check by running "#ls -l /lib/firmware" after booting EVM.
    Please refer to below as reference.


    Best Regards,
    Sudheer

  • Hi Sudheer.

    As far as I checked, main_r5f0 binary is linked like below

    ls -l /lib/firmware/
    lrwxrwxrwx 1 root root 65 Oct 21 2024 j7200-main-r5f0_0-fw -> /lib/firmware/ti-eth/j7200/app_remoteswitchcfg_server_strip.xer5f
    lrwxrwxrwx 1 root root 72 Oct 21 2024 j7200-main-r5f0_0-fw-sec -> /lib/firmware/ti-eth/j7200/app_remoteswitchcfg_server_strip.xer5f.signed

    So I deleted link and boot again, but it failed initialize Ethernet port like below.

    [    1.658490] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
    [    1.671261] am65-cpsw-nuss c000000.ethernet: Use random MAC address
    [    1.677524] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
    [    1.684644] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
    [    1.690969] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
    [    2.326716] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
    [    2.339714] am65-cpsw-nuss c000000.ethernet: Use random MAC address
    [    2.345996] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
    [    2.353148] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
    [    2.359672] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
    [    2.370672] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 60
    [    5.170256] am65-cpsw-nuss c000000.ethernet: PSI-L request err -22
    [    5.196431] am65-cpsw-nuss c000000.ethernet eth0: PHY [c000f00.mdio:00] driver [TI DP83867] (irq=POLL)
    [    5.223209] am65-cpsw-nuss c000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
    [    9.316771] am65-cpsw-nuss c000000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/t

    I also grep am65-cpsw-nuss in EVM which uses MCU_CPWS.

    [    1.354106] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    1.366974] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    1.374183] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    1.384647] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
    [    2.091073] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
    [    2.103944] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
    [    2.111154] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
    [    2.121672] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
    [    2.133162] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
    [    5.640770] am65-cpsw-nuss 46000000.ethernet eth0: PHY [46000f00.mdio:00] driver [TI DP83867] (irq=POLL)
    [    5.664887] am65-cpsw-nuss 46000000.ethernet eth0: configuring for phy/rgmii-rxid link mode

    The main difference is my board report "PSI-L request err -22"

    I also tried to disable MCU_CPWS initialization in uboot by disabling CONFIG_TI_AM65_CPSW_NUSS, but it also failed.

    Please find uboot log below.

    U-Boot 2023.04-g6813f29e-dirty (Oct 21 2024 - 16:59:03 +0900)
    
    SoC:   J7200 SR2.0 GP
    Model: Texas Instruments K3 J7200 SoC
    DRAM:  2 GiB (effective 4 GiB)
    Core:  80 devices, 31 uclasses, devicetree: separate
    Flash: 0 Bytes
    MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
    Loading Environment from MMC... OK
    In:    serial@2800000
    Out:   serial@2800000
    Err:   serial@2800000
    Net:   No ethernet found.
    Hit any key to stop autoboot:  0

    BR

    Jace

  • Hi Sudheer.

    I found that r5 FW is loaded in uboot as well. (run boot_rprocs command in uboot)

    I finally succeeded to initialize Ethernet port correctly after delete it.

    Thank you for your support

    BR

    Jace

     

  • Hi Sudheer.

    Even Ethernet port configured without error. Ping does not work.

    There are RX/TX packets in ifconfig but, no response via ping command.

    BR

    Jace

  • Hi,

    Even Ethernet port configured without error. Ping does not work.

    There are RX/TX packets in ifconfig but, no response via ping command.

    It may be issue with Tx & RX delay in RGMII.

    Please refer to FAQ [How to configure the RGMII delay], and check with your hardware team whether RGMII delay taken care in H/W schematics or not? and configure the "phy-mode" as required.

    Best Regards,
    Sudheer

  • Hi Sudheer.

    When we check RX/TX packet via tcpdump, it can receive rx packets. but tx packets does not transmitted correctly

    Please find the test condition and  tcpdump cature in test board below.

    - Test board (IP : 192.168.250.100. MAC : 7A:2E:D6:C3:2E:C4)

    - EVM (IP : 192.168.250.101)

    ----------------------------------------------------------------------------------------------------------------------------

    7:44:09.022596 ARP, Request who-has j7200-evm tell 192.168.250.101, length 46  <<== Packet received correctly
    17:44:09.022638 ARP, Reply j7200-evm is-at 7a:2e:d6:c3:2e:c4 (oui Unknown), length 28 <<== Try to send response packet

    - But EVM could not receive ARP Reply.

    -----------------------------------------------------------------------------------------------------------------------------

    When we check the status of eth0 via ethtool, it was set correctly like below.

    root@j7200-evm:~# ethtool eth0
    Settings for eth0:
            Supported ports: [ TP    MII ]
            Supported link modes:   10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Full
            Supported pause frame use: Symmetric
            Supports auto-negotiation: Yes
            Supported FEC modes: Not reported
            Advertised link modes:  10baseT/Half 10baseT/Full
                                    100baseT/Half 100baseT/Full
                                    1000baseT/Full
            Advertised pause frame use: Symmetric
            Advertised auto-negotiation: Yes
            Advertised FEC modes: Not reported
            Link partner advertised link modes:  10baseT/Half 10baseT/Full
                                                 100baseT/Half 100baseT/Full
                                                 1000baseT/Full
            Link partner advertised pause frame use: Symmetric
            Link partner advertised auto-negotiation: Yes
            Link partner advertised FEC modes: Not reported
            Speed: 1000Mb/s
            Duplex: Full
            Auto-negotiation: on
            master-slave cfg: preferred slave
            master-slave status: slave
            Port: Twisted Pair
            PHYAD: 0
            Transceiver: external
            MDI-X: Unknown
            Supports Wake-on: ubgs
            Wake-on: d
            SecureOn password: 00:00:00:00:00:00
            Current message level: 0x000020f7 (8439)
                                   drv probe link ifdown ifup rx_err tx_err hw

    When we checked RGMII1_TXC, it was not 125MHz. It was 119Mhz ~ 121MHz

    (We checked the RGMII1_TXC after separating it from PHY by removing serial register.)

    RGMII1_RXC was 125MHz which was sent from PHY.

    This seems to be the main reason why it could receive rx packet only.

    Is there anything I should check ?

    BR

    Jace

  • Hi,

    Have you tried phy-mode as "rgmii-id"?

    Can you please share log of below command, after booting the board.
    #k3conf dump clock 19

    Check the log whether RGMII_MHZ_250_CLK is 250000000Hz. If so, Please check your schematic has any capacitance added to the lanes so downgrading the frequency.

    Please compare with TI EVMs schematic for reference.

    Best Regards,
    Sudheer

  • Hi Sudheer

    Please find my answer below.

    Have you tried phy-mode as "rgmii-id"?

    - I've tried rgmii-id, but there was no effect.

    Please find k3conf.log below

    root@j7200-evm:~/temp/linux# ./k3conf dump clock 19
    |------------------------------------------------------------------------------|
    | VERSION INFO                                                                 |
    |------------------------------------------------------------------------------|
    | K3CONF | (version v0.1-88-g982f5c2 built Wed Mar 15 10:49:12 IST 2023)       |
    | SoC    | J7200 SR2.0                                                         |
    | SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.2.4--v09.02.04 (Kool Koala))') |
    |------------------------------------------------------------------------------|
    
    |------------------------------------------------------------------------------------------------------------------------------------|
    | Device ID | Clock ID | Clock Name                                                              | Status          | Clock Frequency |
    |------------------------------------------------------------------------------------------------------------------------------------|
    |    19     |     0    | DEV_CPSW0_MDIO_MDCLK_O                                                  | CLK_STATE_READY | 0               |
    |    19     |     1    | DEV_CPSW0_GMII3_MT_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |     2    | DEV_CPSW0_GMII2_MR_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |     3    | DEV_CPSW0_SERDES4_RXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |     4    | DEV_CPSW0_CPTS_GENF0                                                    | CLK_STATE_READY | 0               |
    |    19     |     5    | DEV_CPSW0_PRE_RGMII4_TCLK                                               | CLK_STATE_READY | 0               |
    |    19     |     6    | DEV_CPSW0_RGMII3_RXC_I                                                  | CLK_STATE_READY | 0               |
    |    19     |     7    | DEV_CPSW0_RGMII4_RXC_I                                                  | CLK_STATE_READY | 0               |
    |    19     |     8    | DEV_CPSW0_PRE_RGMII3_TCLK                                               | CLK_STATE_READY | 0               |
    |    19     |     9    | DEV_CPSW0_RGMII1_RXC_I                                                  | CLK_STATE_READY | 0               |
    |    19     |    10    | DEV_CPSW0_RGMII_MHZ_250_CLK                                             | CLK_STATE_READY | 250000000       |
    |    19     |    11    | DEV_CPSW0_GMII4_MT_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |    13    | DEV_CPSW0_GMII3_MR_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |    14    | DEV_CPSW0_SERDES4_RXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    15    | DEV_CPSW0_CPTS_RFT_CLK                                                  | CLK_STATE_READY | 200000000       |
    |    19     |    16    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | CLK_STATE_READY | 200000000       |
    |    19     |    17    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV2_16FFT_MAIN_0_HSDIVOUT6_CLK       | CLK_STATE_READY | 200000000       |
    |    19     |    18    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | CLK_STATE_READY | 0               |
    |    19     |    19    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | CLK_STATE_READY | 0               |
    |    19     |    20    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | CLK_STATE_READY | 0               |
    |    19     |    21    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | CLK_STATE_READY | 0               |
    |    19     |    22    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN0_TXMCLK        | CLK_STATE_READY | 0               |
    |    19     |    23    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN1_TXMCLK        | CLK_STATE_READY | 0               |
    |    19     |    24    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN2_TXMCLK        | CLK_STATE_READY | 0               |
    |    19     |    25    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_1_IP2_LN3_TXMCLK        | CLK_STATE_READY | 0               |
    |    19     |    30    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | CLK_STATE_READY | 500000000       |
    |    19     |    31    | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000       |
    |    19     |    32    | DEV_CPSW0_SERDES1_TXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    33    | DEV_CPSW0_CPPI_CLK_CLK                                                  | CLK_STATE_READY | 320000000       |
    |    19     |    34    | DEV_CPSW0_SERDES2_RXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    35    | DEV_CPSW0_SERDES1_RXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    36    | DEV_CPSW0_GMII_RFT_CLK                                                  | CLK_STATE_READY | 125000000       |
    |    19     |    37    | DEV_CPSW0_SERDES1_TXMCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    38    | DEV_CPSW0_SERDES1_REFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    39    | DEV_CPSW0_RMII_MHZ_50_CLK                                               | CLK_STATE_READY | 0               |
    |    19     |    40    | DEV_CPSW0_GMII4_MR_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |    41    | DEV_CPSW0_RGMII_MHZ_50_CLK                                              | CLK_STATE_READY | 50000000        |
    |    19     |    42    | DEV_CPSW0_SERDES3_TXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    43    | DEV_CPSW0_SERDES3_RXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    45    | DEV_CPSW0_PRE_RGMII2_TCLK                                               | CLK_STATE_READY | 0               |
    |    19     |    46    | DEV_CPSW0_SERDES2_TXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    47    | DEV_CPSW0_SERDES1_RXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    48    | DEV_CPSW0_SERDES1_TXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    49    | DEV_CPSW0_RGMII2_RXC_I                                                  | CLK_STATE_READY | 0               |
    |    19     |    50    | DEV_CPSW0_SERDES2_TXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    51    | DEV_CPSW0_PRE_RGMII1_TCLK                                               | CLK_STATE_READY | 0               |
    |    19     |    52    | DEV_CPSW0_RGMII_MHZ_5_CLK                                               | CLK_STATE_READY | 5000000         |
    |    19     |    53    | DEV_CPSW0_GMII2_MT_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |    54    | DEV_CPSW0_SERDES4_TXMCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    55    | DEV_CPSW0_SERDES3_TXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    56    | DEV_CPSW0_SERDES2_TXMCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    57    | DEV_CPSW0_GMII1_MR_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |    58    | DEV_CPSW0_SERDES4_REFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    59    | DEV_CPSW0_SERDES3_TXMCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    60    | DEV_CPSW0_SERDES2_REFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    61    | DEV_CPSW0_SERDES3_REFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    62    | DEV_CPSW0_SERDES3_RXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    63    | DEV_CPSW0_GMII1_MT_CLK                                                  | CLK_STATE_READY | 25000000        |
    |    19     |    64    | DEV_CPSW0_SERDES2_RXFCLK                                                | CLK_STATE_READY | 0               |
    |    19     |    66    | DEV_CPSW0_SERDES4_TXCLK                                                 | CLK_STATE_READY | 0               |
    |    19     |    67    | DEV_CPSW0_SERDES4_TXFCLK                                                | CLK_STATE_READY | 0               |
    |------------------------------------------------------------------------------------------------------------------------------------|
    

    As far as I checked,  RGMII_MHZ_250_CLK is 250000000Hz

    |    19     |    10    | DEV_CPSW0_RGMII_MHZ_250_CLK                                             | CLK_STATE_READY | 250000000       |

    BR

    Jace

     

  • Hi,

    Have you tried phy-mode as "rgmii-id"?

    - I've tried rgmii-id, but there was no effect.

    Ok. Thanks for the confirmation.

    As far as I checked,  RGMII_MHZ_250_CLK is 250000000Hz

    |    19     |    10    | DEV_CPSW0_RGMII_MHZ_250_CLK                                             | CLK_STATE_READY | 250000000       |

    Yes, it seems 250MHz clock supplied to RGMII. H/W will output 125MHz clock on RGMII TxC lines.

    Can you please confirm the schematic for RGMII interface, for reference please refer to TI EVM Design files (schematics) from ti DRA821 page.
    https://www.ti.com/tool/J7200XSOMXEVM

    Best Regards,
    Sudheer