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PROCESSOR-SDK-J722S: J722S MCU domain GPIO input interrupt registration

bingxian lu
Intellectual 570 points
Part Number: PROCESSOR-SDK-J722S
Other Parts Discussed in Thread: TDA4VL, TDA4VM

Tool/software:

Hi,

I found a big difference between TDA4VEN and TDA4VM/TDA4VL GPIO source code when developing the MCU domain GPIO input interrupt. The differences I have found so far are as follows:


1. In the mcu_plus_sdk_j722s_10_00_00_25/test/drivers/gpio path, only the hardware interrupt register is enabled, and the freertos interrupt registration code is not displayed. How can we set up the callback function to enter the callback function when GPIO generates an interrupt?

2, McU_plus_sdk_j722s_10_00_00_25 / test/drivers/gpio/where v0 / gpio. C path no about SCI part code (TDA4VM/VL register interrupt is about SCI related code)


3. The TRM and other related documents provided by TI do not clearly state the interrupt number of GPIO. (For example, if I want to register an interrupt for GPIO1_10 of the MAIN domain in the MCU domain, what should the interrupt number be?)

To sum up, we would like to know how to register GPIO interrupts (including GPIO of MAIN domain) in TDA4VEN MCU domain and enter our registered callback function when an interrupt is generated

Regards,

Bingxian

  • 0
    TI__Genius 13950 points

    Hi Bingxian,

    Can you please provide the GPIO and interrupt setup and initialization you have done?

    Thanks,

    Neehar

  • 0 in reply to Neehar Sawant
    Intellectual 570 points

    Hi Neehar

    The code I am using now is the sample code in the SDK, the path is as follows:

    ti-processor-sdk-rtos-j722s-evm-10_00_00_05/mcu_plus_sdk_j722s_10_00_00_25/test/drivers/gpio

    You can see that there is no registration of interrupt and interrupt callback

    Regards,

    Bingxian

  • 0 in reply to Neehar Sawant
    Intellectual 570 points

    Hi Neehar

    I checked the SDK online documentation

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j722s/10_00_00_05/exports/docs/mcu_plus_sdk_j722s_10_00_00_25/docs/api_guide_j722s/MAIN_DOMAIN_PERIPHERAL_FROM_MCU.html 

    The above link seems to indicate that MCU domain does not support interrupt routing of MAIN/WKUP domain, and only supports polling to query interrupt. Please help confirm whether we cannot register GPIO interrupt of MAIN domain in MCU domain?

    Regards,

    Bingxian

  • 0 in reply to bingxian lu
    TI__Genius 13950 points

    Hi Bingxian,

    Let me look into this and get back to you tomorrow.

    Thanks,

    Neehar

  • +1 in reply to bingxian lu
    TI__Expert 8071 points

    Hi Bingxian,

        Here is an example low lever register wire for gpio_mux interrupt router. 

        MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG  baseaddr: 0xA00000

        WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG  baseaddr :0x4210000

       MCU domain gpio usage

            Example 1：MCU_GPIO0_GPIO_2 to  GPIOMUX_Interrup_out4

              Volatile *(unsigned int*)(0x4210000 + 0x4+(4*0x4)) = 0x10002

           Example2： set wkup GPIO BANK0 for bank interrupt

             Volatile *(unsigned int *)(0x4210000 + 0x4+(*0x4) )= 0x1001e

          The interrupt number is 104.

         Main domain GPIO routing usage,

            MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG  

            Example1: GPIO0_GPIO_2 set to output 34

                Volatile *( unsigned int*)(0xA00000 +  0x4+(34*0x4)) = 0x10002

          Example2  GPIO0_GPIO_BANK_0 output to 34

                Volatile *( unsigned int*)(0xA00000 +  0x4+(34*0x4)) = 0x100BE

         The interrupt number is 32

        About the interrupt register, I suppose it should be same as before .

        As to the SW architecture is different, maybe some development process is different than before. Any help needed, please feedback.

        Thanks.

    Linjun

  • 0 in reply to Linjun Meng
    Intellectual 570 points

    Hi Linjun

    7380.gel_log.txt

    Regards,

    Bingxian

  • 0 in reply to bingxian lu
    TI__Genius 13950 points

    Hi Bingxian,

    Thanks for these logs, I will look through these and get back to you.

    Thanks,

    Neehar

  • 0 in reply to Linjun Meng
    Expert 2030 points

    Hi Chris,

    I want to know what `Volatile *(unsigned int*)(0x4210000 + 0x4+(4*0x4)) = 0x10002` means?
    0x4210000 is the baseaddr of WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG, Why 0x4+(4*0x4))  is GPIOMUX_Interrup_out4? How to understand it? I can't find GPIOMUX_Interrup_out4 in the datasheet. 

    Best regard

  • 0 in reply to xie jc
    TI__Genius 12540 points

    Hello, 

    Please expect a short delay in response.

    Thank you,
    Sarabesh S.

  • 0 in reply to xie jc
    TI__Expert 8071 points

    Dear customer, 

        This ticket is base on the other customer's specific requirement. If you have question, please submit a ticket for it. Thanks.

    Linjun

  • 0 in reply to xie jc
    Expert 2030 points

    Hi Chris,

    Whether the GPIO0_32 ~ GPIO0_64 can't be routed to the GPIOMUX_Interrup? I can't see it in the WKUP_MCU_GPIOMUX_INTROUTER0_INTERRUPT_MAP.

  • 0 in reply to xie jc
    TI__Expert 8071 points

    Dear customer.

         Please check the 10.4.27 MCU_R5FSS0_CORE0_INTERRUPT_MAP.

         MCU_R5FSS0_CORE0_CPU0_INTR_IN_32  is connect to MAIN_GPIOMUX_INTROUTER0_OUTP_34

        MCU_R5FSS0_CORE0_CPU0_INTR_IN_33   is connect to MAIN_GPIOMUX_INTROUTER0_OUTP_35,

         You can connect the GPIO bank2 to MAIN_GPIOMUX_INTROUTER0_OUTP_34, GPIO_BANK3 to MAIN_GPIOMUX_INTROUTER0_OUTP_35.

        Note here, the whole bank share an interrupt NO.

        Thanks.

    Linjun