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DM6467 GPIO control clock source

sumiko
Intellectual 2060 points

Champs,

I need to clarify the function of DM6467 GPIO clock.

The GPIO TRM( sprueq8a) says "The input clock to the GPIO peripheral represents PLL0 divided by 6. The maximum operation speed for
the GPIO peripheral is 10 MHZ."

On the contrary, datasheet(SPRS403G) says (7.28.3 GPIO data timing) that GPIO output minimum pulse is SYSCLK3 period. This means GPIO is controlled by the PLL0 clock divided by 4.

Is the GPIO TRM description wrong ?

Please let me clarify .

Thanks and Regards,

Sumiko Yamaji

 

  • 0
    TI__Expert 8260 points

    Sumiko,

    Thanks for catching this. The GPIO TRM is wrong (sprueq8a). Datasheet is correct. GPIO clock is SYSCLK3, which is PLL0 clock divide by 4. We will correct this in the TRM.

    Regards, Srirami.

  • 0 in reply to srirami
    TI__Intellectual 2060 points

    Thanks Srirami,

    My question has been cleard. But before closing this thread , please let me clarify one more.

    The original inquiry from the customer is that they faces the issue that unexpected signal output happens when initializing GPIO.

    - the GPIO pin is originally hi-z , but externally pulled-up.

    - the customer initializes the GPIO as output "High".

    - But during initalizing, the GPIO pins goes to "Low" for some period.

    - If inserting some delay before GPIO DIR register (from input mode to output mode), the unexpected Low pulse disappear.

    - The customer needs to know what delay would be required in order to avoid unexpexted Low pulse output.

     

    Because GPIO is controlled by SYSCLK3 (CPU clock devided by 4) , it is guessed that OUTDATA register change requires 4 CPU clock, Direction logic change requires 4 CPU clock . Do you think 8 CPU clock delay is enough for avoiding the unexpeted Low pulse output ? Or more additional delay required ?

    Thanks and Regards,

    Sumiko Yamaji

     

  • 0 in reply to sumiko
    TI__Expert 5475 points

    Hello Yamaji-san,

    I am replying based on the spec content. The Reset value for the Direction register should be Input. You mentioned that the pin is pulled high. So, I am assuming that the state of the pin was high from the start and I am not sure as to how the delay helped. I am trying to contact the spec owner to get an accurate response to your question. In the mean time, please let me know your initialization procedure (just the part where you initialize the GPIO registers; do not need interrupt related or bank related info).

    I want to make sure that I understand exactly as to where you have inserted the delay.

    Thank you and best regards, Zegeye