Part Number: AM62A7-Q1
Tool/software:
Hi Expert,
My customer reports an issue about TPS6593 power off sequence issue,
previously the NVM revison is 0x0, and the power off sequence is followed below (orderlyOff).
Now the new PMIC NVM revision change to 0x05. and the power off sequence change to immediateOff, power off in the same time. can you help look into this? is there any impact to AM62A?
Biao
Hello Biao,
From looking at the assembly code between REV0 (on the right) & REV5 (on the left), you can see below, there are no changes on the triggers therefor no changes on the impact of the AM62AX. So if a problem that caused an orderly shutdown in REV0, would cause an orderly shutdown in REV5 as well.
If the customer is seeing a different shutdown sequence in the event of an error then the source of the shutdown is different as there is no other way to cause that.
Best Regards,
Nicholas McNamara
We used the same power off method for two projects, but tested the power off timing differently. Can you help confirm if the simultaneous power off timing will have any impact on AM62A
Hello ??_?, Biao,
I'm assuming this about the difference of 1.2ms for the oscilloscope on the right.
So these are two different projects, so two different boards, but have the same method of shutdown.
Now while we can focus on the differences hardware wise I think it's better to look at the shutdown method. If it's possible to readback the PMIC on the I2C bus after the failure the interrupts (registers: 0x5A - 0x6C) would confirm what I believe to be true.
In the code that refers to the programming on the PMIC, I stated the source for a shutdown is the same regardless of the revision. From the time stamp on the oscilloscope left with the photo all rails: BUCK123 (VDD_CORE), LDO3 (VDDR_CORE), & BUCK4 (VDDS_DDR) to the one of the right taken directly from the screen, the left one has all rails going immediately down which indicates an immediate shutdown as VDD_CORE and VDDR_CORE would normally by 10ms apart. The right has the difference of 1.2ms, hence the question, where does this come from?
What is occurring on the right may be an orderly shutdown that goes into an immediate shutdown during the orderly, hence the 1.2ms difference between VDD_CORE & [VDDR_CORE_VDDS_DDR]. As the priority of Immediate shutdown supersedes an orderly shutdown and can interrupt. See the following trigger priority list and immediate setting in the TRIG_SET command.
Best Regards,
Nicholas McNamara
