DM8148: Question on AMMU of M3

That is possible and it requires some special treatments.

Please refer to the how SDK does similar thing in the below link.

Basically, For a 512MB system, 2 system address spaces of length 512MB are created and map to the same physical memory. On Media Controllers, the first address range(0x80000000) is used to access DDR with cache enabled and the second address(0xA0000000) is used to access the same DDR with cache disabled.

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_Board

This should give your the ideal how to configure your system.

Regards,

yihe

Yihe,

Thanks. We can configure same physical memory to be cache and non-cache now.

Now we have new question. When A8 downloaded the M3 code, will it use the physical address or virtual address?

When we build the M3 code, I think we used physical address. For some address we want to it be cached, and some need to be non-cached. How to make this work?

Hi Chris,

M3 has few registers to map the physical address to logical address (virtual address). So M3 will always use the logical address to access code and data.  There are registers with which you can specify whether the range of logical addresses will be cached or non-cached. Granularity is very high compare to 4K in high level processors. We have register for mapping 4 512MB pages, 2 medium pages of 256KB each and 10 small pages of 4KB each. You can set each page as cacheable or non cacheable but not the part of the page.

Regards,

Hardik Shah

Hardik,

Do you mean when we made M3 code, the memory map in the code is based on virtual address?

Hi,

Yes its a virtual memories. But since its one to one mapping between virtual and physical memories. They both look same.

Regards,

Hardik Shah

Hardik,

If we made the M3 code based on virtual address, how A8 to download the M3 code to DDR as A8 don't know the M3's AMMU config?

Does the M3 bios code config AMMU register before main funciton?

If we made the M3 code based on physical address, when BIOS goes to main function, how it sets the PC pointer as one physical address has mapped to two virtual address?

Hi Chris,

For downloading the code from A8 to M3, we use slave loader and syslink. In syslink we have to configure physical to virtual mapping for loading the binaries. Its defined in $syslink/packages/ti/syslink/samples/hlos/slaveLoader/ti81xx_memmap.txt file. M3 AMMU is configured by syslink based on address mapping we give in the ti81xx_memmpa.txt.

PC is always sets to virtual address and each variable, code will have unique virtual address. Now different virutal address may map to same physical address and in this case your code will crash or behave in weird fashion.

Regards,

Hardik Shah