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AM625: Reset Circuit - Latest Advice (taking into account Errata)?

Brendan O'Brien
Prodigy 50 points

Part Number: AM625

Tool/software:

Hello,

We are doing last steps to prepare our schematic for layout and would appreciate feedback on reset.

Taking into account the i2407 errata for this processor (suggesting to not use MCU_RESETz or MCU_RESETSTATz), is our implementation acceptable?

We had seen some advice to use an AND gate between PORz_OUT and RESETSTATz. This did not make sensse to us because both signals appear to be generated from the same events and do the same thing.

Does this really need to be implemented? 

Does TI see any issues with how we have decided to implement the reset circuit?

Here is a schematic excerpt:

 

  • 0
    TI__Guru**** 234255 points


    Hello Brendan O'Brien

    The schematics you have shown is not complete.

    MCU_PORz 

    I see the JTAG input and the PMIC input.

    I assume the required pulls for the inputs are available.

    It is recommended to add a pulldown at the output of the ANDing logic connected to MCU_PORz.

    A small cap 22 pF is recommended as an option to filter any possible noise seem by the MCU-PORz that could cause the reset input to glitch.

    RESETSTATz

    Using warm reset status output to reset the peripherals is a valid option.

    You need to verify the IO level compatibility.

    We are recommending a pulldown at the output of RESETSTATz to hold the attached device in reset during SOC reset or supply ramp.

    Regards,

    Sreenivasa