SK-AM68: Code Composer Studio 12.8.1 can't connect to SK-AM68 target via Blackhawk XDS560v2-USB System Trace Emulator

Another observation: when the error dialog for "Unable to access the DAP" is up, the XDS560's USB LED toggles quickly between green and red.

Hello TS,

Have you seen the following FAQ?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1178240/faq-sk-tda4vm-how-do-i-connect-the-external-debugger-blackhawk-usb560v2-xds560v2-usb-system-trace-to-the-jtag-on-the-board

Might help.

-Josue

Josue,

Thanks for the reply.  No, I haven't looked at that FAQ, but it's looking like the instructions I linked above are out-of-date or don't actually apply to the J721S2.  Instead of connecting to the first APU, I should have connected to MCU_R5_0.  That didn't work for me originally, but after resetting the board I can connect to MCU_R5_0 consistently.

Are there updated instructions for loading SPL/U-boot to the J721S2 via JTAG?  I've rebuilt things and when I try to Load Memory with "u-boot-spl-dtb.bin" to address 0x41c00000, I hit the following error:

"MCU_Cortex_R5_0: Trouble Writing Memory Block at 0x41c2ffa0 on Page 0 of Length 0x7ff0: (Error -2130 @ 0x41C2FFA0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.0.0.3178)"

At least, I assume I'm loading the correct things to the correct location while connected to the correct core.

HI TS,

First off, if you are not already on CCS 12.8.x, please upgrade to it. There were some known issues with some of the J7x device device files on Linux.

Assuming you are on CCS 12.8.x:

T S said:

I've selected the J721S2_TDA4VL.ccxml Target Configuration.  I've confirmed that "Test Connection" completes successfully. 

This indicates that the low level JTAG connection between the debugger to the device appears fine.

T S said:

When I attempt to connect to the CortexA72_0_0 core, however, I run into one of two problems.  Either CCS simply hangs and I have kill the related process, or I see the following error reported:

The hang is concerning. I suspect the debugger is unable to connect to the A72 due to some target configuration issue but instead of gracefully failing, it hangs trying. If you can reproduce on a consistent basis, please generate a debug server log so we can try to investigate the root cause of the hang:

https://software-dl.ti.com/ccs/esd/documents/ccs_diagnostic-logs.html

The other emulation errors are likely related to the target being in an incorrect state.

Ki,

I'm running CCS 12.8.1.

When the CCS process has hung and I've killed it, the next launch of CCS generates a bug report submission dialog.  I've submitted a trace via this dialog yesterday.  Hopefully this submission is in someone's inbox.  I'll work to get it back in the hung state and submit a bug report via the link you provided above.

Are you saying that I should be able to connect to the Cortex_A72_0_0 core?  I was thinking that because I could connect to the MCU_Cortex_R5_0 core, and that's how the bootloader initially loads things, that maybe my understanding was off and that I could start running SPL operations beginning with that.  

Here's my current setup/workflow... maybe you can see where I'm going off the rails.

- CCS 12.8.1

- Build u-boot via the Top-Level Makefile for SDK 9.2 with "make u-boot"

- Boot the AM68-SK with the micro SD removed and the bootmode set to JTAG (SW1-1 = ON, other switches set to off)

- Launch CCS and connect to MCU_Cortex_R5_0

- Tools > Load Memory to load "u-boot-spl-with-dtb.bin" as a binary (not TI Raw Data)

- Run > Load > Load symbols..." to load "u-boot-spl"

- Set PC to 0x41c00000

- Hit the run button

- Wait briefly

- Hit suspend button

- Observe that execution is stuck at bootstage_error().  Trace: _main > board_init_f > k3_spl_init > preloader_console_int > serial_init > serial_find_console_or_panic > panic_str > panic_finish > hang

I would assume this would generate u-boot-spl console text, but I don't see anything on the serial port.

T S said:

When the CCS process has hung and I've killed it, the next launch of CCS generates a bug report submission dialog.  I've submitted a trace via this dialog yesterday.  Hopefully this submission is in someone's inbox.

Can you attach the same file to this thread? Also note that this file is different from the debug server log. The log is actually more useful so if you can generate this log, that would be very helpful.

T S said:

Are you saying that I should be able to connect to the Cortex_A72_0_0 core?

Actually, I really don't know. My expertise is on the tools itself, not the device/board. Since you have basic JTAG communication working, it appears that the issue is with the board configuration but I don't really know what the proper sequence is to put the board in the proper state for debug. I will defer to the device experts here.

Do you have a private location where I can post the logs?  They contain personally identifiable information that I'd prefer not to post publicly.

I can finally connect to the CortexA72_0_0 core if i do the following:

- configure the AM68-SK with bootmode configured for UART

- sx -kb --xmodem tiboot3.bin < /dev/ttyUSB5 > /dev/ttyUSB5

- sx -kb --ymodem tispl.bin < /dev/ttyUSB6 > /dev/ttyUSB6

- sx -kb --ymodem u-boot.img < /dev/ttyUSB6 > /dev/ttyUSB6

- launch CCS

- Target Configuration > J721S2_TDA4VL.ccxml selected > Right-click > Launch Selected Configuration

- Right-click on the CortexA7_0_0 > Connect Target

This is great.  But, downloading those files over UART is extremely slow.  Isn't there a way to do any of that via JTAG+CCS?

I know I've marked this as resolved, but if this is the case then why does this page imply that it's possible to deploy U-boot over JTAG: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j721s2/10_00_00_08/exports/docs/linux/Foundational_Components/U-Boot/Apps-Load-in-CCS.html

It's misleading.  You can't connect to the Cortex-A72 core.  You can't directly deploy a functioning SPL via JTAG.  Reference my comment above about how deploying the u-boot-spl-with-dtb.bin to the Cortex-R5 results in hitting panic_finish() -> hang().

It goes back to my earlier comment where that page is out-of-date / does not apply to the J721S2.