AM3352: About VLAN ID 0 with 802.1p priority tag

Daniel Cheng1

Mastermind 7075 points

Part Number: AM3352

Tool/software:

Hi Expert,

SOC:AM3352

SDK:06_03_00_106

Linux Kernel:4.19.94

The customer board has two LAN ports, so the device tree is set to dual emac, and the default VIDs are 1 and 2 respectively.

When setting up a VLAN, the VLAN interface (such as eth0.100) generated by using the vconfig add command can send VLAN packets normally.

However, when setting VLAN ID 0 (such as eth0.0), the packets sent will not carry VLAN tags, but in applications, packets with VLAN ID 0 but with priority tags will be required.

CPSW driver's default default VLAN vid=0 is untagged.

Is there a way to make eth0.0 carry VLAN tag vid=0, but the packets sent by eth0 do not carry VLAN tag?

CPSW The following code sets VID 0 as the default VLAN

static int cpsw_ndo_open(struct net_device *ndev)

{

....

/* Add default VLAN */
if (!cpsw->data.dual_emac)
cpsw_add_default_vlan(priv);
else
cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);

}

If the default vlan (vid = 0) is not set, then generally the packets entering and exiting eth0 and eth1 will carry the vlan tag of vlan vid=0

But what the customer wants is that eth0 and eth1 do not have tags, but the new eth0.0 added by vconfig has the tag of vlan vid=0
Because CPSW dual emac mode must require VLAN to distinguish port0/port1, and the default vlan is vid=0

Can the functions requested by customers be realized?

Thanks

Daniel

10 months ago

0 Schuyler Patton 10 months ago

TI__Mastermind 40080 points

Hi,

This should be configurable in the DTS file for the board. Could you please attach the customer DTS file?

I will also request the development team review this e2e post. Please note this will take some time to respond as the development will be out of office until 11/4

Best Regards,

Schuyler

0 Daniel Cheng1 10 months ago in reply to Schuyler Patton

Mastermind 7075 points

Hi Schuyler

I think the configuration in DTS is for dual emac mode to assign VLAN ID for CPSW to distinguish 2 ports.

And we assign VLAN 1 and VLAN 2 to it. If it is not assigned, CPSW driver will automatically assigned VLAN1 and VLAN2 to it.

in cpsw.c cpsw_probe_dt function:

...

if (data->dual_emac) {
if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
&prop)) {
dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
slave_data->dual_emac_res_vlan = i+1;
dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
slave_data->dual_emac_res_vlan, i);
} else {
slave_data->dual_emac_res_vlan = prop;
}
}

...

I attached our device tree file for your reference.

However, I think it is nothing related to the issue that we need to sending out packet with VLAN tag vid 0 on "eth0.0" that generated by "vconfig add eth0 0".

And the packet send out by eth0 base interface will not have VLAN tag.

Thanks

Daniel

Fullscreen am335x-nts8600.txt Download

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "ATOP NTS8600";
	compatible = "ti,am335x-evm", "ti,am33xx";
	
	aliases {
		emmc = &mmc2;        
    };

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	device {
		clocks = <&pcf8563>; 
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>; /* 512 MB */
	};

	chosen {
		stdout-path = &uart0;
		/*tick-timer = &timer1;*/
	};	
		
	vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1351500>;
			regulator-boot-on;
			regulator-always-on;
	};
		
	vmmcsd_fixed: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	buzzer: buzzer {
		compatible = "atop_buzzer";
		pinctrl-names = "default";
		pinctrl-0 = <&atop_buzz>;
		gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
	};

	reset_btn: reset_btn {
		label = "reset_btn";
		compatible = "atop_reset_button";
		pinctrl-names = "default";
		pinctrl-0 = <&atop_reset_sw>;
		debounce-interval = <10>;
		gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
	};

	watchdog {
		compatible = "atop_watchdog";
		pinctrl-names = "default";
		pinctrl-0 = <&atop_wdt>;
		gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
	};

	pwr_det {
		compatible = "atop,pow_detect";
		pinctrl-names = "default";
		pinctrl-0 = <&atop_cpu_power>;
		gpio-num = <2>;				/* number of power detect pins */
		gpio-pw = <&gpio3 2 0>;		/* PWR1 */
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&gpio_led>;
		run_led {
			label = "run_led";
			gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;		/* Active low */
			linux,default-trigger = "none";
		};
		gnss_led {
			label = "gnss_led";
			gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;		/* Active low */
			linux,default-trigger = "none";
		};
		alm_led {
			label = "alm_led";
			gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;            /* Active low */
			linux,default-trigger = "none";
                };
    };
};

&am33xx_pinmux {	
    pinctrl-names = "default";

	atop_buzz: pinmux_atop_buzz_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */
		>;
	};

	atop_wdt: pinmux_atop_wdt_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x9a4, PIN_INPUT_PULLUP | MUX_MODE7) /* (C13) mcasp0_fsr.gpio3[19] */
		>;
	};

	atop_cpu_power: pinmux_atop_cpu_power_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE7) /* (J15) gmii1_rxer.gpio3[2] */
		>;
	};

	atop_reset_sw: pinmux_atop_reset_sw_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLUP | MUX_MODE7) /* (D13) mcasp0_axr1.gpio3[20] */
		>;
	};

	gpio_led: pinmux_gpio_led_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x8e0, PIN_INPUT | MUX_MODE7) /* (U5) lcd_vsync.gpio2[22] */
			AM33XX_IOPAD(0x8e4, PIN_INPUT | MUX_MODE7) /* (R5) lcd_hsync.gpio2[23] */
			AM33XX_IOPAD(0x8e8, PIN_INPUT | MUX_MODE7) /* (V5) lcd_pclk.gpio2[24] */
		>;
	};

	i2c0_pins: i2c0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
		>;
	};

	i2c1_pins: i2c1_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* (A16) spi0_cs0.I2C1_SCL */
			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* (B16) spi0_d1.I2C1_SDA */
		>;
	};
	
	i2c2_pins: i2c2_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* (B17) spi0_d0.I2C2_SCL */
			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* (A17) spi0_sclk.I2C2_SDA */
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)   /* mdio_data.mdio_data */
			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)          /* mdio_clk.mdio_clk */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

	mmc1_pins_default: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
			AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] mmc0 cd*/
		>;
	};

	mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
	pinctrl-single,pins = <
		AM33XX_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
			AM33XX_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
			AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7) /* (H18) rmii1_refclk.gpio0[29] mmc0 cd*/
		>;
	};

	emmc1_pins_default: emmc1_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */
			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */
			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */
			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */
			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */
			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */
			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */
			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */
			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */
			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */
		>;
	};

	cpsw_default: rgmii1_pins_default {
		pinctrl-single,pins = <
		  /* rmii1 */
			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (J16) gmii1_txen.rgmii1_tctl */
			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (J17) gmii1_rxdv.rgmii1_rctl */
			AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (K18) gmii1_txclk.rgmii1_tclk */
			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (L18) gmii1_rxclk.rgmii1_rclk */
			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (K17) gmii1_txd0.rgmii1_td0 */
			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (K16) gmii1_txd1.rgmii1_td1 */
			AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (K15) gmii1_txd2.rgmii1_td2 */
			AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (J18) gmii1_txd3.rgmii1_td3 */
			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (M16) gmii1_rxd0.rgmii1_rd0 */
			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (L15) gmii1_rxd1.rgmii1_rd1 */
			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (L16) gmii1_rxd2.rgmii1_rd2 */
			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (L17) gmii1_rxd3.rgmii1_rd3 */
			/* rmii2 */
			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (R13) gpmc_a0.rgmii2_tctl */
			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (V14) gpmc_a1.rgmii2_rctl */
			AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (U15) gpmc_a6.rgmii2_tclk */
			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (T15) gpmc_a7.rgmii2_rclk */
			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (V15) gpmc_a5.rgmii2_td0 */
			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (R14) gpmc_a4.rgmii2_td1 */
			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (T14) gpmc_a3.rgmii2_td2 */
			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* (U14) gpmc_a2.rgmii2_td3 */
			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (V17) gpmc_a11.rgmii2_rd0 */
			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (T16) gpmc_a10.rgmii2_rd1 */
			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (U16) gpmc_a9.rgmii2_rd2 */
			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (V16) gpmc_a8.rgmii2_rd3 */
		>;
	};

	/* Optional sleep pin settings. Must manually enter values in the below skeleton. */
	cpsw_sleep: rgmii1_pins_sleep {
		pinctrl-single,pins = <
		  /* rmii1 */
			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J16) gmii1_txen.rgmii1_tctl */
			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J17) gmii1_rxdv.rgmii1_rctl */
			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K18) gmii1_txclk.rgmii1_tclk */
			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L18) gmii1_rxclk.rgmii1_rclk */
			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K17) gmii1_txd0.rgmii1_td0 */
			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K16) gmii1_txd1.rgmii1_td1 */
			AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K15) gmii1_txd2.rgmii1_td2 */
			AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J18) gmii1_txd3.rgmii1_td3 */
			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (M16) gmii1_rxd0.rgmii1_rd0 */
			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L15) gmii1_rxd1.rgmii1_rd1 */
			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L16) gmii1_rxd2.rgmii1_rd2 */
			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L17) gmii1_rxd3.rgmii1_rd3 */
			/* rmii2 */
			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (R13) gpmc_a0.rgmii2_tctl */
			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (V14) gpmc_a1.rgmii2_rctl */
			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (U15) gpmc_a6.rgmii2_tclk */
			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (T15) gpmc_a7.rgmii2_rclk */
			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (V15) gpmc_a5.rgmii2_td0 */
			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7  ) /* (R14) gpmc_a4.rgmii2_td1 */
			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (T14) gpmc_a3.rgmii2_td2 */
			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (U14) gpmc_a2.rgmii2_td3 */
			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (V17) gpmc_a11.rgmii2_rd0 */
			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (T16) gpmc_a10.rgmii2_rd1 */
			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (U16) gpmc_a9.rgmii2_rd2 */
			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (V16) gpmc_a8.rgmii2_rd3 */
		>;
	};

	uart0_pins: uart0_pins_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x970, PIN_INPUT | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */
			AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */
		>;
	};
	
	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */
			AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */
			AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* (D18) uart1_ctsn.uart1_ctsn */
			AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE0) /* (D17) uart1_rtsn.uart1_rtsn */
		>;
	};

	uart4_pins: pinmux_uart4_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* (E18) uart0_ctsn.uart4_rxd */
			AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* (E17) uart0_rtsn.uart4_txd */
		>;
	};

	spi1_pins: pinmux_spi1_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* (A13) mcasp0_aclkx.spi1_sclk */
			AM33XX_IOPAD(0x994, PIN_INPUT | MUX_MODE3) /* (B13) mcasp0_fsx.spi1_d0 */
			AM33XX_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
			AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
		>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;

	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;

	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins>;
    
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	status = "okay";
	clock-frequency = <400000>;

	eeprom0@52 {
		compatible = "atop_eeprom";
		reg = <0x52>;
	};

	eeprom1@53 {
		compatible = "atmel,24c64";
		reg = <0x53>;
	};

	pcf8563: extrtc@51 {
		compatible = "atop_rtc";
		reg = <0x51>;
        };
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <400000>;
	status = "okay";

	cpld@0A {
		compatible = "atop,atop_cpld";
		reg = <0x0A>;
	};

	sfp0@50 {
		compatible = "sff,sfp";
		reg = <0x50>;
	};

	sfp0ex@51 {
		compatible = "sff,sfp";
		reg = <0x51>;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	clock-frequency = <400000>;
	status = "okay";

	gnss@42 {
		compatible = "gnss";
		reg = <0x42>;
	};

	sfp1@50 {
		compatible = "sff,sfp";
		reg = <0x50>;
	};

	sfp1ex@51 {
		compatible = "sff,sfp";
		reg = <0x51>;
	};

	si5383@6C {
		compatible = "atop,si5383";
		reg = <0x6C>;
	};
};

&usb {
	status = "okay";
};

&usb_ctrl_mod {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
	dr_mode = "host";
};

&cppi41dma  {
	status = "okay";
};

&mac {
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_default>;
	/*pinctrl-1 = <&cpsw_sleep>;*/
	/*active_slave = <1>;*/
	status = "okay";
	dual_emac ;
	
};

&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&davinci_mdio_default>;
	/*pinctrl-1 = <&davinci_mdio_sleep>;*/
	status = "okay";
	ethernet-phy@0 {
		compatible = "brcm,bcm54210", "ethernet-phy-ieee802.3-c22";
		device_type = "ethernet-phy";
		reg = <0>;
	};
	ethernet-phy@1 {
		compatible = "brcm,bcm54210", "ethernet-phy-ieee802.3-c22";
		device_type = "ethernet-phy";
		reg = <1>;
	};
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0>;
	phy-mode = "rgmii-id";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rgmii-id";
	dual_emac_res_vlan = <2>;
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <4>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_sleep>;
	cd-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};

&mmc2 {
	vmmc-supply = <&vmmcsd_fixed>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc1_pins_default>;
	bus-width = <8>;
	status = "okay";
	non-removable;
	ti,vcc-aux-disable-is-sleep;
	
	layout@0,0 {
		bank-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "MLO1";
			reg = <0x00000100 0x00000100>;
		};
		partition@1 {
			label = "MLO2";
			reg = <0x00000200 0x00000100>;
		};
		partition@2 {
			label = "u-boot";
			reg = <0x00000300 0x00000700>;
		};
		partition@3 {
			label = "u-boot env";
			reg = <0x00000A00 0x00000100>;
		};
		partition@4 {
			label = "DTB";
			reg = <0x00000B00 0x00000500>;
		};
		partition@5 {
			label = "kernel";
			reg = <0x00001000 0x00005000>;
		};
		partition@6 {
			label = "rootfs";
			reg = <0x00006000 0x00010000>;
		};
	};
	
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	
	ti,spi-num-cs = <1>;
	status = "okay";
	
	tpm_tis@0 {
		compatible = "infineon,slb9670";
		reg = <0>;
		spi-max-frequency = <10000000>;
		/*spi-cpha;*/
		/*spi-cpol;*/
	};
};

&edma {
	ti,edma-xbar-event-map = /bits/ 16 <1 12
					    2 13>;
};

&elm {
	status = "okay";
};


&sham {
	status = "okay";
};

&aes {
	status = "okay";
};

0 Daniel Cheng1 10 months ago in reply to Daniel Cheng1

Mastermind 7075 points

Hi Schuyler

Is there any update on this issue?

Thanks

Daniel

Processors

Processors forum

AM3352: About VLAN ID 0 with 802.1p priority tag