TDA4VM: Is "blanking config of csitx node" work

Pierre Hsieh

Intellectual 945 points

Part Number: TDA4VM

Tool/software:

Hi,

We used psdk_0804.

j7_csitx.h

uint32_t vBlank; /*!< Vertical blanking in terms of number of line. */

We think the blanking should be a fixed value when set vBlank.
But the blanking is not fixed as below.

Is "blanking config of csitx node" work ?
How could we set the blanking ?

Regards,

1 month ago

0 Brijesh Jadav 1 month ago

TI__Guru**** 430195 points

Pierre,

blanking is not supported for TDA4VM.

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

We used sdk 8.04.

Is new sdk support blanking ?

If yse, what sdk version we need to update ?

Regards,

0 Pierre Hsieh 1 month ago in reply to Pierre Hsieh

Intellectual 945 points

Hi,

is blanking supported for j721s2_evm ?

We used sdk 8.04. Is new sdk support blanking ?

If yse, what sdk version we need to update ?

Regards,

0 Brijesh Jadav 1 month ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Hi Pierre,

No, even 8.04 does not support blanking. but J721S2 does support blanking, but for j721s2, i would recommend using the latest release.

Btw, why do you require blanking from CSITX?

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

We used an ISP to receive the csitx signal from TDA4 and ISP needed a fixed blanking to resolve image.

You mean J721S2 support blanking. but need update new sdk version ?

Regards,

0 Brijesh Jadav 1 month ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Hi Pierre,

Yes, please use the latest release for J721S2.

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

Could you suggest what package we need to update (releate to csitx blanking).

such as "psdk_10_00_00_05\psdk_base\psdk_rtos\pdk_j721s2_10_00_00_27\packages\ti\drv\csitx".

Regards,

0 Brijesh Jadav 1 month ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Mainly CSITX driver and CSL folder for the CSITX.

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

We update two folder:

psdk_10_00_00_05\psdk_base\psdk_rtos\pdk_j721s2_10_00_00_27\packages\ti\drv\csitx\

psdk_10_00_00_05\psdk_base\psdk_rtos\pdk_j721s2_10_00_00_27\packages\ti\csl\src\ip\csitx\

Some def file:

psdk_rtos/pdk_j721s2_08_04_00_20/packages/ti/csl/csl_csitx.h

psdk_rtos/pdk_j721s2_08_04_00_20/packages/ti/csl/csl_fvid2_dataTypes.h

psdk_rtos/pdk_j721s2_08_04_00_20/packages/ti/csl/src/ip/udmap/V0/csl_udmap_tr.h

psdk_rtos/pdk_j721s2_08_04_00_20/packages/ti/csl/tistdtypes.h

The blanking (vBlank) is still not a fixed value.

Are more files need to be updated ?

Regards,

0 Pierre Hsieh 1 month ago in reply to Pierre Hsieh

Intellectual 945 points

Hi,

for some config :

Main_CSI_Tx_0:dphy_TxByteClkHS_cl_clk

Main_CSI_Tx_0:main_clk_clk

Main_CSI_Tx_0:vbus_clk_clk

How to check default value and set value for them ?

Regards,

0 Brijesh Jadav 1 month ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Sorry which default value do you want to check? do you mean clock? but why do you want to check the default clock value?

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Pierre Hsieh

Intellectual 945 points

Hi,

https://sir.ext.ti.com/jira/browse/EXT_EP-11372

Cloud we get the patch ?

referent to the patch, maybe we can know what files need to porting.

Regards,

0 Brijesh Jadav 1 month ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Please apply attached patch on pdk/packages/ti/drv/csitx folder.

/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_PDK_2D00_12630_2D00_Configure_2D00_vBlank_2D00_and_2D00_hBlank_2D00_values_2D00_to_2D00_CSIT.patch

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

We porting csitx of drv and csl from pdk_j721s2_10_00_00_27. And add some trace log.

//log

We think the value of vBlank is currently being written to the corresponding register when get retVal=0.

But the blanking signal is still not a fixed value from using oscilloscope.

Will the blanking signal been a fixed value if set vBlank succeed ?

We have no idea about how to set a fixed blanking for every frames.

is more register need to set ?

Regards,

0 Pierre Hsieh 1 month ago in reply to Pierre Hsieh

Intellectual 945 points

Hi,

In our test. Application call vxProcessGraph once will trigger update csitx buffer and hw send csitx signal (a frame) once as below.

The blanking is a fixed value (equal to vBlank) if call vxProcessGraph with 33ms cycle.

But application is hard to call vxProcessGraph with 33ms cycle steadily (because OS schedule).

If any delay, the blanking will be not a fixed value (will be vBlank + IdleBlank).

Is any way we can set csitx hw to send signal with 33ms cycle steadily as below ?

Can we set frame rate (30 fps) for csitx node/drv/hw ?

Can hw auto send csitx signal (with its own buffer) with 33ms cycle steadily ?

(not triggered by application call vxProcessGraph. maybe vxProcessGraph just update csitx buffer)

Regards,

0 Pierre Hsieh 1 month ago in reply to Pierre Hsieh

Intellectual 945 points

Hi,

We used an ISP to receive output signal of CSITX. The ISP ask frame rate 30 Hz (every frame is 33ms, blanking is the same).
Can CSITX support this ?
If not, could you help to explain that how output signal of CSITX work.

Regards,

0 Brijesh Jadav 1 month ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Hi,

CSITX outputs the data as it receives, so if you want the frame to be output at 30fps, you need to send the frames at this rate..

Regards,

Brijesh

0 Pierre Hsieh 1 month ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

Compare to DSI. DSI seems to support 30Hz.
Could you help to explain that how output signal of DSI work.

Regards,

0 Terry wu 1 month ago in reply to Brijesh Jadav

Intellectual 320 points

Hi Brijesh,

How to start a timer?expires every 33ms and generates a callback and in this callback.

Could you please help us tell our software people(Pierre Hsieh )?

-- 
Thanks.
Best Regards.

0 Terry wu 30 days ago in reply to Brijesh Jadav

Intellectual 320 points

Hi Brijesh,

The waveform output by TDA4 CSItx measured with an oscilloscope is as below video:

The CSItx sometimes outputs 2 frames continuously

-- 
Thanks.
Best Regards.

0 Brijesh Jadav 30 days ago in reply to Terry wu

TI__Guru**** 430195 points

Hi Terry,

You could configure timer to generate callback at every 33ms, ie can configure to run it periodic..

Regards,

Brijesh

0 Pierre Hsieh 29 days ago in reply to Brijesh Jadav

Intellectual 945 points

Hi,

Could you help to review the timer_create we used.

main_test_csitx.c

/**
 *
 *
 */
#include <linux/prctl.h>  /* Definition of PR_* constants */
#include <sys/prctl.h>
#include <unistd.h> /* for usleep */

#include "app_common.h"
#include <VX/vxu.h>
#include <utils/perf_stats/include/app_perf_stats.h>
#include <TI/j7_kernels_imaging_aewb.h>
#include <TI/tivx_mutex.h>
#include "app_sensor_module.h"
#include "app_capture_module.h"


#define NUM_CHANNELS        		(1U)
#define CSITX_INST_ID       		(0U)
#define CSITX_INST_ID_1       		(1U)
#define CSITX_LANE_BAND_SPEED       (TIVX_CSITX_LANE_BAND_SPEED_390_TO_450_MBPS)//(TIVX_CSITX_LANE_BAND_SPEED_770_TO_870_MBPS)
#define CSIRX_LANE_BAND_SPEED       (TIVX_CAPTURE_LANE_BAND_SPEED_720_TO_800_MBPS)
#define CSITX_LANE_SPEED_MBPS       (477U)//(392U)//(600)
#define VIDEO_PIPE_NUM              (4u)
#define _PIPE_MODE                  (1u)
#define _MAX_CSITX_NODE             (2u)
#define _ENABLIE_MULTI_CSITX_NODE   (1u)

#define TEST_IMG_W          (1920u)
#define TEST_IMG_H          (1280u)
#define TEST_FILE_PATH      (256u)

typedef struct
{
	vx_context context;
    vx_graph graph;
	vx_graph graph_csitx;

	SensorObj     sensorObj;
	CaptureObj    captureObj;

	vx_object_array input_image_arr[_MAX_CSITX_NODE];

	vx_node csitx_node;
	vx_node csitx_node_2;
	vx_user_data_object csitx_config;
	vx_user_data_object csitx_config2;
		;
	int32_t lPipeNum;
	uint32_t ulEnqueueCnt;
	//
	tivx_task task;
    vx_uint32 stop_task;
    vx_uint32 stop_task_done;
	//
	tivx_task task_csitx;
    vx_uint32 stop_task_csitx;
    vx_uint32 stop_task_done_csitx;
	//
	app_perf_point_t stTimeLog_Put;
	app_perf_point_t stTimeLog_Get;
	app_perf_point_t stTimeLog_CsiTx;

	tivx_mutex mtxHndlState;
	uint8_t ucNewFrameIn;
} appTestCsiTxInfo_t;

extern uint64_t appLogGetTimeInUsec();


static appTestCsiTxInfo_t g_stTestCsiTxInfo = {0};

static void app_parameter_by_node_index(vx_graph graph, vx_node node, vx_uint32 node_parameter_index)
{
    vx_parameter parameter = vxGetParameterByIndex(node, node_parameter_index);

    vxAddParameterToGraph(graph, parameter);
    vxReleaseParameter(&parameter);
}

static int32_t app_put_csitx_data(vx_reference frame_set[])
{
	appTestCsiTxInfo_t *obj = &g_stTestCsiTxInfo;
//	uint32_t i;
	
	tivxMutexLock(obj->mtxHndlState);
	appPerfPointBegin(&obj->stTimeLog_Put);
	if (frame_set[0])
	{
		vx_image dst_img = (vx_image)vxGetObjectArrayItem(obj->input_image_arr[0], 1);

		//
		vxuSwapImageHandle_oToBrite((vx_image)frame_set[0], dst_img);
		//
		vxReleaseImage(&dst_img);
		//
		obj->ucNewFrameIn = 1;
	}

	if (_ENABLIE_MULTI_CSITX_NODE && (frame_set[1]))
	{
		vx_image dst_img = (vx_image)vxGetObjectArrayItem(obj->input_image_arr[1], 1);

		//
		vxuSwapImageHandle_oToBrite((vx_image)frame_set[1], dst_img);
		//
		vxReleaseImage(&dst_img);
		//
		obj->ucNewFrameIn = 1;
	}
	appPerfPointEnd(&obj->stTimeLog_Put);
	tivxMutexUnlock(obj->mtxHndlState);
	return 0;
}

void app_get_csitx_img(appTestCsiTxInfo_t *obj, uint32_t idx)
{
	tivxMutexLock(obj->mtxHndlState);

	if (1 == obj->ucNewFrameIn)
	{
		appPerfPointBegin(&obj->stTimeLog_Get);
		
		vx_image old_img = (vx_image)vxGetObjectArrayItem(obj->input_image_arr[0], 0);
		vx_image new_img = (vx_image)vxGetObjectArrayItem(obj->input_image_arr[0], 1);

		//
		vxuSwapImageHandle_oToBrite(old_img, new_img);
		vxReleaseImage(&old_img);
		vxReleaseImage(&new_img);
		

		if (_ENABLIE_MULTI_CSITX_NODE)
		{
			old_img = (vx_image)vxGetObjectArrayItem(obj->input_image_arr[1], 0);
			new_img = (vx_image)vxGetObjectArrayItem(obj->input_image_arr[1], 1);

			//
			vxuSwapImageHandle_oToBrite(old_img, new_img);
			vxReleaseImage(&old_img);
			vxReleaseImage(&new_img);
		}
		//reset
		obj->ucNewFrameIn = 0;

		appPerfPointEnd(&obj->stTimeLog_Get);
	}
	tivxMutexUnlock(obj->mtxHndlState);
}

static int g_randomSleep = 0;
#include <time.h>   /* for nanosleep */

static void app_run_csitx_task(void *app_var)
{
	appTestCsiTxInfo_t *obj = (appTestCsiTxInfo_t *)app_var;
	uint64_t ts_us, te_us;
	int64_t interval_us;

	prctl(PR_SET_NAME, "CSI_TX_Tsk");
	appLogPrintf("Run csi-tx graph start !!!!!!!!!!!!!!!!!!!\n");
	while (1 && !obj->stop_task_csitx)
	{
		//appPerfPointBegin(&obj->stTimeLog_CsiTx);
		ts_us = appLogGetTimeInUsec();
		//vxProcessGraph(obj->graph_csitx);
		//Get new frame
		app_get_csitx_img(obj, 0);
		te_us = appLogGetTimeInUsec();

		if (te_us > ts_us)
			interval_us = (te_us - ts_us); // us -> ms
		else
			interval_us = ((0xFFFFFFFFFFFFFFFFu - te_us) + ts_us) / 1000u; //us -> ms

		int64_t sleepTime = 33333;
		if(g_randomSleep == 1)
		{
			static int random = 0;
			random += 7;
			sleepTime += ((random%32)-16)*1000;
		}

		if (interval_us < sleepTime)
		{
			//usleep((sleepTime - interval_us));
			
			struct timespec delay_time, remain_time;
			int ret;
			
			delay_time.tv_sec  = 0;
			delay_time.tv_nsec = ((sleepTime - interval_us))*1000;
			
			do
			{
				ret = nanosleep(&delay_time, &remain_time);
				if(ret < 0 && remain_time.tv_sec > 0 && remain_time.tv_nsec > 0)
				{
					/* restart for remaining time */
					delay_time = remain_time;
				}
				else
				{
					break;
				}
			} while(1);

		}
			
		
		//appPerfPointEnd(&obj->stTimeLog_CsiTx);

		#if 0
		uint64_t tmp  = appLogGetTimeInUsec() - obj->stTimeLog_CsiTx.tmp;
		if(tmp > 35000)
		{
			appLogPrintf("@@@ tmp=%lu\n", tmp);
		}
		#endif
	}

	appLogPrintf("Run csi-tx graph end !!!!!!!!!!!!!!!!!!!\n");
	obj->stop_task_done_csitx = 1;
}

static void app_run_graph_task(void *app_var)
{
	appTestCsiTxInfo_t *obj = (appTestCsiTxInfo_t *)app_var;
	uint32_t i;

	//read test image;
	//app_read_test_img(obj);

	prctl(PR_SET_NAME, "Capture_Tsk");
	appLogPrintf("Run video graph start !!!!!!!!!!!!!!!!!!!\n");
	appStartImageSensor(obj->sensorObj.sensor_name, obj->sensorObj.ch_mask);
	while (!obj->stop_task)
	{
		if (_PIPE_MODE)
		{
			if (obj->lPipeNum < 0)
			{
				//read test image;
				//app_read_test_img(obj, obj->ulEnqueueCnt);
				vxGraphParameterEnqueueReadyRef(obj->graph, 0, (vx_reference*)&obj->captureObj.raw_image_arr[obj->ulEnqueueCnt], 1);

				++obj->ulEnqueueCnt;
				++obj->lPipeNum;
				//if (0 == obj->lPipeNum)
				//	tivxTaskWaitMsecs(33*VIDEO_PIPE_NUM);
			}
			else
			{
				vx_object_array csitx_input_arr;
				uint32_t num_refs;
				vx_reference frame_set[8] = {NULL};

				//dequeu
				vxGraphParameterDequeueDoneRef(obj->graph, 0, (vx_reference*)&csitx_input_arr, 1, &num_refs);
				//Put data
				frame_set[0] = vxGetObjectArrayItem(csitx_input_arr, 0);
				frame_set[1] = vxGetObjectArrayItem(csitx_input_arr, 1);
				app_put_csitx_data(frame_set);
				for (i = 0; i < 8; ++i)
				{
					if (frame_set[i])
						vxReleaseImage((vx_image*)&frame_set[i]);
				}
				//equeue
				vxGraphParameterEnqueueReadyRef(obj->graph, 0, (vx_reference*)&csitx_input_arr, 1);

				++obj->ulEnqueueCnt;
				++obj->lPipeNum;

				obj->ulEnqueueCnt %= VIDEO_PIPE_NUM;
				//tivxTaskWaitMsecs(33);
			}
		}
		else
		{
			vxProcessGraph(obj->graph);
			tivxTaskWaitMsecs(33);
		}

	}
	if (_PIPE_MODE)
	{
		vxWaitGraph(obj->graph);
	}
	appStopImageSensor(obj->sensorObj.sensor_name, obj->sensorObj.ch_mask);
	appLogPrintf("Run video graph end !!!!!!!!!!!!!!!!!!!\n");
	obj->stop_task_done = 1;
}

static void app_test_csitx_run(appTestCsiTxInfo_t *obj)
{
	char c;

	do
	{
		c = getchar();

		if ('x' == c)
			break;
		else if('s' == c)
		{
			app_get_csitx_img(obj, 0);
			vxProcessGraph(obj->graph_csitx);
		}
		else if('r' == c)
		{
			g_randomSleep = (g_randomSleep + 1) % 2;
			printf("g_randomSleep=%d\n", g_randomSleep);
		}
		else if ('p' == c)
		{
			#if 0
			appPerfStatsPrintAll();
			#endif
			tivx_utils_graph_perf_print(obj->graph);
			printf("\n");
			tivx_utils_graph_perf_print(obj->graph_csitx);
			printf("\n");
			appPerfPointPrint(&obj->stTimeLog_Get);
			appPerfPointPrint(&obj->stTimeLog_Put);
			appPerfPointPrint(&obj->stTimeLog_CsiTx);
			printf("\n");
			#if 0
			vx_reference refs[1];
			refs[0] = (vx_reference)obj->captureObj.raw_image_arr[0];
			tivxNodeSendCommand(obj->captureObj.node, 0u,
							TIVX_CAPTURE_PRINT_STATISTICS,
							refs, 1u);
			#endif

			//tivxNodeSendCommand(obj->csitx_node, 0u,
			//				TIVX_CAPTURE_PRINT_STATISTICS,
			//				refs, 1u);
		}

	} while (1);
	//
	obj->stop_task = 1;
	obj->stop_task_csitx = 1;
	while (!obj->stop_task_done)
		tivxTaskWaitMsecs(33);
	while (!obj->stop_task_done_csitx)
		tivxTaskWaitMsecs(33);
}

#if 1
#include <signal.h> 
#include <time.h> 

static uint64_t PRE_ts_us = 0;

void timer_thread(union sigval v) 
{ 
	//printf("@@@ =%lu\n", appLogGetTimeInUsec() - XXX_ts_us);
	uint64_t tmp = appLogGetTimeInUsec() - PRE_ts_us;
	
	PRE_ts_us = appLogGetTimeInUsec();

	appTestCsiTxInfo_t *obj = &g_stTestCsiTxInfo;

	appPerfPointBegin(&obj->stTimeLog_CsiTx);
	
	//app_get_csitx_img(obj, 0);
	vxProcessGraph(obj->graph_csitx);

	appPerfPointEnd(&obj->stTimeLog_CsiTx);

#if 1
	if(tmp > 34000 || tmp < 32000)
	{
		appLogPrintf("@@@ tmp=%lu\n", tmp);
	}
	#endif
} 
#endif

int app_test_csitx_main(vx_int32 argc, vx_char* argv[])
{
#if 1
    timer_t timerid; 
    struct sigevent evp; 
    memset(&evp, 0, sizeof(struct sigevent));       //清零初始化 

    evp.sigev_value.sival_int = 111;                //也是标识定时器的，回调函数可以获得 
    evp.sigev_notify = SIGEV_THREAD;                //线程通知的方式，派驻新线程 
    evp.sigev_notify_function = timer_thread;       //线程函数地址 

    if (timer_create(CLOCK_REALTIME, &evp, &timerid) == -1) 
    {   
        perror("fail to timer_create"); 
        exit(-1); 
    }   

    /* 第一次间隔it.it_value这么长,以后每次都是it.it_interval这么长,就是说it.it_value变0的时候会>装载it.it_interval的值 */
    struct itimerspec it; 
    it.it_interval.tv_sec = 0;//1;  // 回调函数执行频率为1s运行1次
    it.it_interval.tv_nsec = 33 * 1000 * 1000; 
    it.it_value.tv_sec = 20;     // 倒计时3秒开始调用回调函数
    it.it_value.tv_nsec = 0; 

    if (timer_settime(timerid, 0, &it, NULL) == -1) 
    {   
        perror("fail to timer_settime"); 
        exit(-1); 
    }   
#endif

	vx_status status;
	appTestCsiTxInfo_t *obj = &g_stTestCsiTxInfo;
	uint32_t i;

	status = tivxMutexCreate(&obj->mtxHndlState);
	if (VX_SUCCESS != status)
	{
		appLogPrintf("Create mutext fail !!!!!!!!!!!!!!!!!!!!!!!\n");
		return 0;
	}
	appPerfPointSetName(&obj->stTimeLog_Put, "PutData");
	appPerfPointReset(&obj->stTimeLog_Put);
	appPerfPointSetName(&obj->stTimeLog_Get, "GetData");
	appPerfPointReset(&obj->stTimeLog_Get);
	appPerfPointSetName(&obj->stTimeLog_CsiTx, "CsiTxProc");
	appPerfPointReset(&obj->stTimeLog_CsiTx);

	obj->context = vxCreateContext();
	tivxHwaLoadKernels(obj->context);
	tivxImagingLoadKernels(obj->context);
	obj->graph = vxCreateGraph(obj->context);
	obj->graph_csitx = vxCreateGraph(obj->context);

	obj->sensorObj.is_interactive = 0;
	obj->sensorObj.sensor_index = 6; //TI-913
	obj->sensorObj.num_cameras_enabled = 2;
	obj->sensorObj.ch_mask = 0x0C;
	status = app_querry_sensor(&obj->sensorObj);
	if (VX_SUCCESS != status)
	{
		appLogPrintf("app_querry_sensor fail !!\n");
		goto __exit;
	}
	appLogPrintf("Sensor name : %s, %ux%u, ch_mask = 0x%X \n", obj->sensorObj.sensor_name, obj->sensorObj.image_width, obj->sensorObj.image_height, obj->sensorObj.ch_mask);
	obj->captureObj.capture_format = 1;
	obj->captureObj.enable_error_detection = 1;
	app_init_sensor(&obj->sensorObj, "sensor_obj");
	app_init_capture(obj->context, &obj->captureObj, &obj->sensorObj, "capture_obj", VIDEO_PIPE_NUM);

	//ceate resource for csitx graph
	vx_image exemplar = vxCreateImage(obj->context, obj->sensorObj.image_width, obj->sensorObj.image_height, VX_DF_IMAGE_UYVY);
	for (i = 0; i < _MAX_CSITX_NODE; i++)
	{
		obj->input_image_arr[i] = vxCreateObjectArray(obj->context, (vx_reference)exemplar, 2); //0 : for graph process, 1 : for backup image
	}
	vxReleaseImage(&exemplar);
	//reset parameter
	obj->lPipeNum = -VIDEO_PIPE_NUM;
	obj->ulEnqueueCnt = 0;

	///create video graph
	app_create_graph_capture(obj->graph, &obj->captureObj);
	//setup pipe mode
	if (_PIPE_MODE)
	{
		uint32_t graph_parameter_index = 0;
		vx_graph_parameter_queue_params_t graph_parameters_queue_params_list[6];

		app_parameter_by_node_index(obj->graph, obj->captureObj.node, 1);
		graph_parameters_queue_params_list[graph_parameter_index].graph_parameter_index = graph_parameter_index;
	    graph_parameters_queue_params_list[graph_parameter_index].refs_list_size = VIDEO_PIPE_NUM;
	    graph_parameters_queue_params_list[graph_parameter_index].refs_list = (vx_reference*)&obj->captureObj.raw_image_arr[0];
	    graph_parameter_index++;

		status = vxSetGraphScheduleConfig(obj->graph,
                VX_GRAPH_SCHEDULE_MODE_QUEUE_AUTO,
                graph_parameter_index,
                graph_parameters_queue_params_list);
		if (VX_SUCCESS == status)
		{
			 status = tivxSetGraphPipelineDepth(obj->graph, VIDEO_PIPE_NUM);
			 if (VX_SUCCESS != status)
			 	appLogPrintf("tivxSetGraphPipelineDepth fail !!\n");
		}
	}
	
	//ceate csitx#1
	
    tivx_csitx_params_t local_csitx_config;
	uint32_t loopCnt;
	tivx_csitx_params_init(&local_csitx_config);
	local_csitx_config.numInst							= 1U;
	local_csitx_config.numCh							= NUM_CHANNELS;
	local_csitx_config.instId[0U]						= CSITX_INST_ID;
	local_csitx_config.instCfg[0U].rxCompEnable 		= (uint32_t)vx_true_e;
	local_csitx_config.instCfg[0U].rxv1p3MapEnable		= (uint32_t)vx_true_e;
	local_csitx_config.instCfg[0U].laneBandSpeed		= CSITX_LANE_BAND_SPEED;
	local_csitx_config.instCfg[0U].laneSpeedMbps		= CSITX_LANE_SPEED_MBPS;
	local_csitx_config.instCfg[0U].numDataLanes 		= 2U;//4U;
	for (loopCnt = 0U ;
		loopCnt < local_csitx_config.instCfg[0U].numDataLanes ;
		loopCnt++)
	{
		local_csitx_config.instCfg[0U].lanePolarityCtrl[loopCnt] = 0u;
	}
	for (loopCnt = 0U; loopCnt < NUM_CHANNELS; loopCnt++)
	{
		local_csitx_config.chVcNum[loopCnt]   = loopCnt;
		local_csitx_config.chInstMap[loopCnt] = CSITX_INST_ID;
	}
	obj->csitx_config = vxCreateUserDataObject(obj->context, "tivx_csitx_params_t", sizeof(tivx_csitx_params_t), &local_csitx_config);
    obj->csitx_node = tivxCsitxNode(obj->graph_csitx, obj->csitx_config, obj->input_image_arr[0]);
	vxSetNodeTarget(obj->csitx_node, VX_TARGET_STRING, TIVX_TARGET_CSITX);
	vxSetReferenceName((vx_reference)obj->csitx_node, "csitx_node_1");
	//ceate csitx#2
	if (_ENABLIE_MULTI_CSITX_NODE)
	{
    	tivx_csitx_params_t local_csitx_config2;
		tivx_csitx_params_init(&local_csitx_config2);
		local_csitx_config2.numInst							= 1U;
		local_csitx_config2.numCh							= NUM_CHANNELS;
		local_csitx_config2.instId[0U]						= CSITX_INST_ID_1;
		local_csitx_config2.instCfg[0U].rxCompEnable 		= (uint32_t)vx_true_e;
		local_csitx_config2.instCfg[0U].rxv1p3MapEnable		= (uint32_t)vx_true_e;
		local_csitx_config2.instCfg[0U].laneBandSpeed		= CSITX_LANE_BAND_SPEED;
		local_csitx_config2.instCfg[0U].laneSpeedMbps		= CSITX_LANE_SPEED_MBPS;
		local_csitx_config2.instCfg[0U].numDataLanes 		= 2U;//4U;
	
		for (loopCnt = 0U ;
			loopCnt < local_csitx_config2.instCfg[0U].numDataLanes ;
			loopCnt++)
		{
			local_csitx_config2.instCfg[0U].lanePolarityCtrl[loopCnt] = 0u;
		}
		for (loopCnt = 0U; loopCnt < NUM_CHANNELS; loopCnt++)
		{
			local_csitx_config2.chVcNum[loopCnt]   = loopCnt;
			local_csitx_config2.chInstMap[loopCnt] = CSITX_INST_ID_1;
		}

		obj->csitx_config2 = vxCreateUserDataObject(obj->context, "tivx_csitx_params_t", sizeof(tivx_csitx_params_t), &local_csitx_config2);
	    obj->csitx_node_2 = tivxCsitxNode(obj->graph_csitx, obj->csitx_config2, obj->input_image_arr[1]);
	    vxSetNodeTarget(obj->csitx_node_2, VX_TARGET_STRING, TIVX_TARGET_CSITX2);
		vxSetReferenceName((vx_reference)obj->csitx_node_2, "csitx_node_2");
	}
	
	//verif all graph
	if (VX_SUCCESS == status)
	{
		status = vxVerifyGraph(obj->graph);
		status |= vxVerifyGraph(obj->graph_csitx);
	}
	if (VX_SUCCESS == status)
	{
		tivx_task_create_params_t params;

		app_send_error_frame(&obj->captureObj);

		//csitx task
		tivxTaskSetDefaultCreateParams(&params);
		params.task_main = app_run_csitx_task;
		params.app_var = (void *)obj;
		obj->stop_task_csitx = 0;
		status |= tivxTaskCreate(&obj->task_csitx, &params);

		//Video task
   	 	tivxTaskSetDefaultCreateParams(&params);
    	params.task_main = app_run_graph_task;
		params.app_var = (void *)obj;
		obj->stop_task = 0;
    	status |= tivxTaskCreate(&obj->task, &params);

		//
		if (VX_SUCCESS == status)
		{
			app_test_csitx_run(obj);
		}
	}
	else
	{
		appLogPrintf("vxVerifyGraph fail !!\n");
	}
	app_delete_capture(&obj->captureObj);
	app_deinit_sensor(&obj->sensorObj);
	app_deinit_capture(&obj->captureObj, VIDEO_PIPE_NUM);
__exit:	
	vxReleaseNode(&obj->csitx_node);
	vxReleaseNode(&obj->csitx_node_2);
	for (i = 0; i < _MAX_CSITX_NODE; i++)
		vxReleaseObjectArray(&obj->input_image_arr[i]);

	tivxImagingUnLoadKernels(obj->context);
	tivxHwaUnLoadKernels(obj->context);
	vxReleaseUserDataObject(&obj->csitx_config);
	vxReleaseUserDataObject(&obj->csitx_config2);
	vxReleaseGraph(&obj->graph);
	vxReleaseGraph(&obj->graph_csitx);
	vxReleaseContext(&obj->context);
	tivxMutexDelete(&obj->mtxHndlState);

	return 0;
}

Sometimes get time diff bigger than 1 ms or more.

timer diff log.txt

[MPU1_0]    129.859005 s: | I | default | @@@ tmp=34726
[MPU1_0]    129.893634 s: | I | default | @@@ tmp=31274
[MPU1_0]    353.269156 s: | I | default | @@@ tmp=35024
[MPU1_0]    353.300170 s: | I | default | @@@ tmp=31031
[MPU1_0]    494.773198 s: | I | default | @@@ tmp=35056
[MPU1_0]    494.804180 s: | I | default | @@@ tmp=31003
[MPU1_0]   1217.406915 s: | I | default | @@@ tmp=34779
[MPU1_0]   1217.438140 s: | I | default | @@@ tmp=31258
[MPU1_0]   1691.187255 s: | I | default | @@@ tmp=34178
[MPU1_0]   1691.219143 s: | I | default | @@@ tmp=31876
[MPU1_0]   1949.808275 s: | I | default | @@@ tmp=34093
[MPU1_0]   1949.840198 s: | I | default | @@@ tmp=31991
[MPU1_0]   2417.815036 s: | I | default | @@@ tmp=34850
[MPU1_0]   2417.846141 s: | I | default | @@@ tmp=31209
[MPU1_0]   2887.569358 s: | I | default | @@@ tmp=34192
[MPU1_0]   2887.601220 s: | I | default | @@@ tmp=31881
[MPU1_0]   3203.709390 s: | I | default | @@@ tmp=34288
[MPU1_0]   3203.741379 s: | I | default | @@@ tmp=31797
[MPU1_0]   3497.808414 s: | I | default | @@@ tmp=37324
[MPU1_0]   3497.837207 s: | I | default | @@@ tmp=28776
[MPU1_0]   3903.804246 s: | I | default | @@@ tmp=34070
[MPU1_0]   3903.836178 s: | I | default | @@@ tmp=31976
[MPU1_0]   3916.312580 s: | I | default | @@@ tmp=35456
[MPU1_0]   3916.343139 s: | I | default | @@@ tmp=30600
[MPU1_0]   4457.941698 s: | I | default | @@@ tmp=35609
[MPU1_0]   4457.972148 s: | I | default | @@@ tmp=30431
[MPU1_0]   4553.805224 s: | I | default | @@@ tmp=34034
[MPU1_0]   5404.776179 s: | I | default | @@@ tmp=34098
[MPU1_0]   5749.956368 s: | I | default | @@@ tmp=34237
[MPU1_0]   5749.988137 s: | I | default | @@@ tmp=31782
[MPU1_0]   5923.701191 s: | I | default | @@@ tmp=34066
[MPU1_0]   5923.733133 s: | I | default | @@@ tmp=31981
[MPU1_0]   6411.804206 s: | I | default | @@@ tmp=34045
[MPU1_0]   6787.840590 s: | I | default | @@@ tmp=35393
[MPU1_0]   6787.871153 s: | I | default | @@@ tmp=30550
[MPU1_0]   6987.622371 s: | I | default | @@@ tmp=35218
[MPU1_0]   6987.653141 s: | I | default | @@@ tmp=30830
[MPU1_0]   7203.804215 s: | I | default | @@@ tmp=34075
[MPU1_0]   7203.836214 s: | I | default | @@@ tmp=31995
[MPU1_0]   7650.030952 s: | I | default | @@@ tmp=34822
[MPU1_0]   7650.062107 s: | I | default | @@@ tmp=31223
[MPU1_0]   7929.804268 s: | I | default | @@@ tmp=34141
[MPU1_0]   7929.836203 s: | I | default | @@@ tmp=31946
[MPU1_0]   8476.978784 s: | I | default | @@@ tmp=35626
[MPU1_0]   8477.009133 s: | I | default | @@@ tmp=30408
[MPU1_0]   8577.000528 s: | I | default | @@@ tmp=34397
[MPU1_0]   8577.032160 s: | I | default | @@@ tmp=31632
[MPU1_0]   8767.113507 s: | I | default | @@@ tmp=34413
[MPU1_0]   8767.145139 s: | I | default | @@@ tmp=31635
[MPU1_0]   8804.272453 s: | I | default | @@@ tmp=35352
[MPU1_0]   8804.303204 s: | I | default | @@@ tmp=30716
[MPU1_0]   8961.814989 s: | I | default | @@@ tmp=35870
[MPU1_0]   8961.845165 s: | I | default | @@@ tmp=30186
[MPU1_0]  10031.806912 s: | I | default | @@@ tmp=35816
[MPU1_0]  10031.837186 s: | I | default | @@@ tmp=30212
[MPU1_0]  10774.206200 s: | I | default | @@@ tmp=34137
[MPU1_0]  10774.238198 s: | I | default | @@@ tmp=31965
[MPU1_0]  10841.823563 s: | I | default | @@@ tmp=34328
[MPU1_0]  10841.855138 s: | I | default | @@@ tmp=31717
[MPU1_0]  11002.302492 s: | I | default | @@@ tmp=34352
[MPU1_0]  11002.334131 s: | I | default | @@@ tmp=31680
[MPU1_0]  11263.266147 s: | I | default | @@@ tmp=34016
[MPU1_0]  11708.733414 s: | I | default | @@@ tmp=34310
[MPU1_0]  11708.765142 s: | I | default | @@@ tmp=31732
[MPU1_0]  12143.805908 s: | I | default | @@@ tmp=34794
[MPU1_0]  12143.837194 s: | I | default | @@@ tmp=31295
[MPU1_0]  12564.060519 s: | I | default | @@@ tmp=34420
[MPU1_0]  12564.092092 s: | I | default | @@@ tmp=31625
[MPU1_0]  12681.804219 s: | I | default | @@@ tmp=34087
[MPU1_0]  12816.840736 s: | I | default | @@@ tmp=34670
[MPU1_0]  12816.872205 s: | I | default | @@@ tmp=31464
[MPU1_0]  13313.821565 s: | I | default | @@@ tmp=35423
[MPU1_0]  13313.852192 s: | I | default | @@@ tmp=30663
[MPU1_0]  13399.422215 s: | I | default | @@@ tmp=34151
[MPU1_0]  13399.454122 s: | I | default | @@@ tmp=31915
[MPU1_0]  13793.805167 s: | I | default | @@@ tmp=34005
[MPU1_0]  14265.804228 s: | I | default | @@@ tmp=34078
[MPU1_0]  14265.836167 s: | I | default | @@@ tmp=31997
[MPU1_0]  14321.806987 s: | I | default | @@@ tmp=35826
[MPU1_0]  14321.837189 s: | I | default | @@@ tmp=30249
[MPU1_0]  14955.803872 s: | I | default | @@@ tmp=36707
[MPU1_0]  14955.833166 s: | I | default | @@@ tmp=29331
[MPU1_0]  15297.054185 s: | I | default | @@@ tmp=34070
[MPU1_0]  15297.086129 s: | I | default | @@@ tmp=31969
[MPU1_0]  15769.812545 s: | I | default | @@@ tmp=34361
[MPU1_0]  15769.844185 s: | I | default | @@@ tmp=31724
[MPU1_0]  15779.845780 s: | I | default | @@@ tmp=35515
[MPU1_0]  15779.876143 s: | I | default | @@@ tmp=30423
[MPU1_0]  16565.838387 s: | I | default | @@@ tmp=34182
[MPU1_0]  16565.870151 s: | I | default | @@@ tmp=31773
[MPU1_0]  17415.820019 s: | I | default | @@@ tmp=34864
[MPU1_0]  17415.851188 s: | I | default | @@@ tmp=31219
[MPU1_0]  17777.961847 s: | I | default | @@@ tmp=34720
[MPU1_0]  17777.993096 s: | I | default | @@@ tmp=31297
[MPU1_0]  17822.973532 s: | I | default | @@@ tmp=34449
[MPU1_0]  17823.005135 s: | I | default | @@@ tmp=31618
[MPU1_0]  17887.554288 s: | I | default | @@@ tmp=34144
[MPU1_0]  17887.586130 s: | I | default | @@@ tmp=31904
[MPU1_0]  18688.233762 s: | I | default | @@@ tmp=34664
[MPU1_0]  18688.265146 s: | I | default | @@@ tmp=31385
[MPU1_0]  18998.632090 s: | I | default | @@@ tmp=34814
[MPU1_0]  18998.663152 s: | I | default | @@@ tmp=31230
[MPU1_0]  19337.806965 s: | I | default | @@@ tmp=35831
[MPU1_0]  19337.837202 s: | I | default | @@@ tmp=30275
[MPU1_0]  19413.144287 s: | I | default | @@@ tmp=34156
[MPU1_0]  19413.176168 s: | I | default | @@@ tmp=31910
[MPU1_0]  19423.178699 s: | I | default | @@@ tmp=36551
[MPU1_0]  19423.208127 s: | I | default | @@@ tmp=29480
[MPU1_0]  20271.804246 s: | I | default | @@@ tmp=34104
[MPU1_0]  20928.703567 s: | I | default | @@@ tmp=35429
[MPU1_0]  20928.734121 s: | I | default | @@@ tmp=30612
[MPU1_0]  21659.586179 s: | I | default | @@@ tmp=34076
[MPU1_0]  21659.618121 s: | I | default | @@@ tmp=31962
[MPU1_0]  22089.972678 s: | I | default | @@@ tmp=34558
[MPU1_0]  22090.004129 s: | I | default | @@@ tmp=31473
[MPU1_0]  22193.328319 s: | I | default | @@@ tmp=34179
[MPU1_0]  22193.360128 s: | I | default | @@@ tmp=31869
[MPU1_0]  22313.811218 s: | I | default | @@@ tmp=34060
[MPU1_0]  22835.673217 s: | I | default | @@@ tmp=34096
[MPU1_0]  22835.705171 s: | I | default | @@@ tmp=31993
[MPU1_0]  22911.804618 s: | I | default | @@@ tmp=34462
[MPU1_0]  22911.836136 s: | I | default | @@@ tmp=31583
[MPU1_0]  23196.990358 s: | I | default | @@@ tmp=34216
[MPU1_0]  23197.022101 s: | I | default | @@@ tmp=31819
[MPU1_0]  23367.633181 s: | I | default | @@@ tmp=34032
[MPU1_0]  23759.047129 s: | I | default | @@@ tmp=35004
[MPU1_0]  23759.078137 s: | I | default | @@@ tmp=31057
[MPU1_0]  24511.842794 s: | I | default | @@@ tmp=34532
[MPU1_0]  24511.874118 s: | I | default | @@@ tmp=31435
[MPU1_0]  25043.803419 s: | I | default | @@@ tmp=35201
[MPU1_0]  25043.834171 s: | I | default | @@@ tmp=30893
[MPU1_0]  25681.824190 s: | I | default | @@@ tmp=34018
[MPU1_0]  25716.838955 s: | I | default | @@@ tmp=35818
[MPU1_0]  25716.869177 s: | I | default | @@@ tmp=30282
[MPU1_0]  26127.753507 s: | I | default | @@@ tmp=34368
[MPU1_0]  26127.785201 s: | I | default | @@@ tmp=31687
[MPU1_0]  26388.717240 s: | I | default | @@@ tmp=34087
[MPU1_0]  26388.749141 s: | I | default | @@@ tmp=31956
[MPU1_0]  26670.768105 s: | I | default | @@@ tmp=34006
[MPU1_0]  27512.862916 s: | I | default | @@@ tmp=34837
[MPU1_0]  27512.894181 s: | I | default | @@@ tmp=31258
[MPU1_0]  27773.826818 s: | I | default | @@@ tmp=34697
[MPU1_0]  27773.858157 s: | I | default | @@@ tmp=31340
[MPU1_0]  27943.809796 s: | I | default | @@@ tmp=34673
[MPU1_0]  27943.841167 s: | I | default | @@@ tmp=31397
[MPU1_0]  27993.804301 s: | I | default | @@@ tmp=34172
[MPU1_0]  27993.836169 s: | I | default | @@@ tmp=31908
[MPU1_0]  28035.814417 s: | I | default | @@@ tmp=35237
[MPU1_0]  28035.845122 s: | I | default | @@@ tmp=30800
[MPU1_0]  28777.489387 s: | I | default | @@@ tmp=35145
[MPU1_0]  28777.520127 s: | I | default | @@@ tmp=30891
[MPU1_0]  29633.805183 s: | I | default | @@@ tmp=34051
[MPU1_0]  29640.670244 s: | I | default | @@@ tmp=35094
[MPU1_0]  29640.701138 s: | I | default | @@@ tmp=30937
[MPU1_0]  29689.810992 s: | I | default | @@@ tmp=38848
[MPU1_0]  29689.840057 s: | I | default | @@@ tmp=29101
[MPU1_0]  29689.871198 s: | I | default | @@@ tmp=31157
[MPU1_0]  29966.874363 s: | I | default | @@@ tmp=34169
[MPU1_0]  29966.906143 s: | I | default | @@@ tmp=31793
[MPU1_0]  30016.605263 s: | I | default | @@@ tmp=34180
[MPU1_0]  30016.637143 s: | I | default | @@@ tmp=31855
[MPU1_0]  30463.689588 s: | I | default | @@@ tmp=34452
[MPU1_0]  30463.721146 s: | I | default | @@@ tmp=31607
[MPU1_0]  30493.818890 s: | I | default | @@@ tmp=34737
[MPU1_0]  30493.850127 s: | I | default | @@@ tmp=31307
[MPU1_0]  30639.810988 s: | I | default | @@@ tmp=34866
[MPU1_0]  30639.842158 s: | I | default | @@@ tmp=31209
[MPU1_0]  30644.332014 s: | I | default | @@@ tmp=34895
[MPU1_0]  30644.363128 s: | I | default | @@@ tmp=31143
[MPU1_0]  32380.692413 s: | I | default | @@@ tmp=34323
[MPU1_0]  32380.724149 s: | I | default | @@@ tmp=31739
[MPU1_0]  32571.399892 s: | I | default | @@@ tmp=34754
[MPU1_0]  32571.431124 s: | I | default | @@@ tmp=31303
[MPU1_0]  33227.439923 s: | I | default | @@@ tmp=34812
[MPU1_0]  33227.471139 s: | I | default | @@@ tmp=31229
[MPU1_0]  33353.070251 s: | I | default | @@@ tmp=34155
[MPU1_0]  33353.102152 s: | I | default | @@@ tmp=31894
[MPU1_0]  33354.258596 s: | I | default | @@@ tmp=34427
[MPU1_0]  33354.290139 s: | I | default | @@@ tmp=31587
[MPU1_0]  33461.809154 s: | I | default | @@@ tmp=38016
[MPU1_0]  33461.839326 s: | I | default | @@@ tmp=30156
[MPU1_0]  33461.870139 s: | I | default | @@@ tmp=30858
[MPU1_0]  33499.822279 s: | I | default | @@@ tmp=35203
[MPU1_0]  33499.853146 s: | I | default | @@@ tmp=30857
[MPU1_0]  33801.804201 s: | I | default | @@@ tmp=34070
[MPU1_0]  34283.802979 s: | I | default | @@@ tmp=34794
[MPU1_0]  34283.834128 s: | I | default | @@@ tmp=31229
[MPU1_0]  34319.805163 s: | I | default | @@@ tmp=34026
[MPU1_0]  34799.824774 s: | I | default | @@@ tmp=35671
[MPU1_0]  34799.855169 s: | I | default | @@@ tmp=30415
[MPU1_0]  36035.805196 s: | I | default | @@@ tmp=34066
[MPU1_0]  36045.804272 s: | I | default | @@@ tmp=34082
[MPU1_0]  36137.808247 s: | I | default | @@@ tmp=34115
[MPU1_0]  36137.840295 s: | I | default | @@@ tmp=31959
[MPU1_0]  36576.082568 s: | I | default | @@@ tmp=35440
[MPU1_0]  36576.113147 s: | I | default | @@@ tmp=30606
[MPU1_0]  39605.812993 s: | I | default | @@@ tmp=35848
[MPU1_0]  39605.843241 s: | I | default | @@@ tmp=30234
[MPU1_0]  39767.775655 s: | I | default | @@@ tmp=34483
[MPU1_0]  39767.807295 s: | I | default | @@@ tmp=31616
[MPU1_0]  39806.980028 s: | I | default | @@@ tmp=34906
[MPU1_0]  39807.011114 s: | I | default | @@@ tmp=31146
[MPU1_0]  40289.802363 s: | I | default | @@@ tmp=34181
[MPU1_0]  40289.834172 s: | I | default | @@@ tmp=31866
[MPU1_0]  40319.833409 s: | I | default | @@@ tmp=35191
[MPU1_0]  40319.864140 s: | I | default | @@@ tmp=30844
[MPU1_0]  41112.757263 s: | I | default | @@@ tmp=35119
[MPU1_0]  41112.788127 s: | I | default | @@@ tmp=30924
[MPU1_0]  41935.776981 s: | I | default | @@@ tmp=34843
[MPU1_0]  41935.808224 s: | I | default | @@@ tmp=31234
[MPU1_0]  42215.816521 s: | I | default | @@@ tmp=36359
[MPU1_0]  42215.846185 s: | I | default | @@@ tmp=29699
[MPU1_0]  43591.817251 s: | I | default | @@@ tmp=36083
[MPU1_0]  43591.847207 s: | I | default | @@@ tmp=29980
[MPU1_0]  43902.973419 s: | I | default | @@@ tmp=35256
[MPU1_0]  43903.004170 s: | I | default | @@@ tmp=30782
[MPU1_0]  44535.285853 s: | I | default | @@@ tmp=34702
[MPU1_0]  44535.317134 s: | I | default | @@@ tmp=31344
[MPU1_0]  45259.008340 s: | I | default | @@@ tmp=34227
[MPU1_0]  45259.040116 s: | I | default | @@@ tmp=31818
[MPU1_0]  45549.045191 s: | I | default | @@@ tmp=34053
[MPU1_0]  46595.805205 s: | I | default | @@@ tmp=34070
[MPU1_0]  46632.996266 s: | I | default | @@@ tmp=34137
[MPU1_0]  46633.028142 s: | I | default | @@@ tmp=31915
[MPU1_0]  46803.804141 s: | I | default | @@@ tmp=34014
[MPU1_0]  46867.461182 s: | I | default | @@@ tmp=34073
[MPU1_0]  46867.493160 s: | I | default | @@@ tmp=31976
[MPU1_0]  47001.804216 s: | I | default | @@@ tmp=34077
[MPU1_0]  47001.836122 s: | I | default | @@@ tmp=31984
[MPU1_0]  47189.805170 s: | I | default | @@@ tmp=34028
[MPU1_0]  47295.406341 s: | I | default | @@@ tmp=35168
[MPU1_0]  47295.437376 s: | I | default | @@@ tmp=30936
[MPU1_0]  47479.810036 s: | I | default | @@@ tmp=34905
[MPU1_0]  47479.841179 s: | I | default | @@@ tmp=31169
[MPU1_0]  48540.033757 s: | I | default | @@@ tmp=34658
[MPU1_0]  48540.065318 s: | I | default | @@@ tmp=31435
[MPU1_0]  48733.809759 s: | I | default | @@@ tmp=34613
[MPU1_0]  48733.841194 s: | I | default | @@@ tmp=31460
[MPU1_0]  48864.226040 s: | I | default | @@@ tmp=34939
[MPU1_0]  48864.257136 s: | I | default | @@@ tmp=31113
[MPU1_0]  48941.810944 s: | I | default | @@@ tmp=36851
[MPU1_0]  48941.840229 s: | I | default | @@@ tmp=29262
[MPU1_0]  48971.805480 s: | I | default | @@@ tmp=34339
[MPU1_0]  48971.837227 s: | I | default | @@@ tmp=31754
[MPU1_0]  49301.807013 s: | I | default | @@@ tmp=35855
[MPU1_0]  49301.837209 s: | I | default | @@@ tmp=30229
[MPU1_0]  49410.243752 s: | I | default | @@@ tmp=34654
[MPU1_0]  49410.275143 s: | I | default | @@@ tmp=31379
[MPU1_0]  49961.805284 s: | I | default | @@@ tmp=34116
[MPU1_0]  50115.816922 s: | I | default | @@@ tmp=34647
[MPU1_0]  50115.848137 s: | I | default | @@@ tmp=31335
[MPU1_0]  50169.804247 s: | I | default | @@@ tmp=34084
[MPU1_0]  50353.450940 s: | I | default | @@@ tmp=35818
[MPU1_0]  50353.481146 s: | I | default | @@@ tmp=30226
[MPU1_0]  51555.804274 s: | I | default | @@@ tmp=34094
[MPU1_0]  51555.836212 s: | I | default | @@@ tmp=31995
[MPU1_0]  51992.692558 s: | I | default | @@@ tmp=35414
[MPU1_0]  51992.723137 s: | I | default | @@@ tmp=30645
[MPU1_0]  52573.823013 s: | I | default | @@@ tmp=35866
[MPU1_0]  52573.853114 s: | I | default | @@@ tmp=30184
[MPU1_0]  53247.286699 s: | I | default | @@@ tmp=35565
[MPU1_0]  53247.317138 s: | I | default | @@@ tmp=30500
[MPU1_0]  53759.181352 s: | I | default | @@@ tmp=34173
[MPU1_0]  53759.213125 s: | I | default | @@@ tmp=31888
[MPU1_0]  54220.853096 s: | I | default | @@@ tmp=35888
[MPU1_0]  54220.883307 s: | I | default | @@@ tmp=30226
[MPU1_0]  54281.111429 s: | I | default | @@@ tmp=36316
[MPU1_0]  54281.141180 s: | I | default | @@@ tmp=29764
[MPU1_0]  55211.808112 s: | I | default | @@@ tmp=34012
[MPU1_0]  55575.865427 s: | I | default | @@@ tmp=35135
[MPU1_0]  55575.896126 s: | I | default | @@@ tmp=30855
[MPU1_0]  55927.149372 s: | I | default | @@@ tmp=34207
[MPU1_0]  55927.181115 s: | I | default | @@@ tmp=31834
[MPU1_0]  56215.206901 s: | I | default | @@@ tmp=34814
[MPU1_0]  56215.238187 s: | I | default | @@@ tmp=31264
[MPU1_0]  57257.808661 s: | I | default | @@@ tmp=34540
[MPU1_0]  57257.840152 s: | I | default | @@@ tmp=31514
[MPU1_0]  57665.822283 s: | I | default | @@@ tmp=36116
[MPU1_0]  57665.852126 s: | I | default | @@@ tmp=29936
[MPU1_0]  57749.805521 s: | I | default | @@@ tmp=34425
[MPU1_0]  57749.870097 s: | I | default | @@@ tmp=31141

Could you help to explain why the diff occur.

Could you suggest what timer is better to be used ? What layer to add the timer ? maybe tiovx or driver ?

Regards,

0 Brijesh Jadav 29 days ago in reply to Pierre Hsieh

TI__Guru**** 430195 points

Hi Pierre,

You are creating timer on Linux, which can vary. I would suggest to create it on R5F and submit the frame at the exact 33ms interval.

But before that, lets understand the issue and entire chain in todays call.

Regards,

Brijesh

Processors

Processors forum

TDA4VM: Is "blanking config of csitx node" work