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PROCESSOR-SDK-AM64X: MCSPI, high edge trigger latch response

Jun Tu
Expert 1320 points
Part Number: PROCESSOR-SDK-AM64X

Tool/software:

Hi, I am using am64x board without OS.

I would like to config   high edge trigger latch response   On D12,    I mean  after the transfer the data, CS will goes to high for 30 ms and goes to low. eg:

Notice, it is not a Standard CS. It should be called LE, latch enable.  How to config LE?


do you have an example?


Thanks,  

  • 0
    TI__Guru**** 166599 points

    Hello Jun Tu, 

    Thank you for the query.

    I do not understand the query. 

    I need you to please explain your use case and the device you are looking to interface.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Expert 1320 points

    • 1. In standard SPI operation, the Chip Select (CS) line is typically either active-high or active-low.

    • 2. In my case, however, CS functions as a LE)signal: it should remain low during normal operation, CS go high for 30 ms after each data transfer, and then return to low.

    CS: chip selector.
    LE: latch enable. 

    which part of the sentance you do not understand? I can further explian. 
    Thanks. 

  • 0 in reply to Jun Tu
    TI__Guru**** 166599 points

    Hello Jun Tu, 

    Thank you.

    Let me check with the team internally.

    Jun Tu said:
    which part of the sentance you do not understand? I can further explian. 

    Help me understand the use case.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Expert 1320 points

    user case:

    eg:
    LE is like CS.   but your CS is either active high and active low. it couldn't do latche enable. as below photo. 

  • 0 in reply to Jun Tu
    TI__Guru**** 166599 points

    Hello Jun Tu, 

    Please refer inputs i received from the expert:

    I don’t understand that E2E thread.

    Also that’s slave a.k.a. device mode operation, right? We don’t officially support that in Linux/

    Looks like the use case you are looking to implement has not been verified.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Genius 3209 points

    Sreenivasa:

     I wonder if something like that "latched SPI" could be done in a PRU block? Might take up valuable resources.

  • 0 in reply to Jim Mrowca
    TI__Guru**** 166599 points

    Hello Jim,

    Thank you.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Expert 1320 points

    hello, Jim:

    just let you know, there are two option to generate latch enabled signal. 

    1. using Force enable mode,   disadvantage:  it only support single channel. if you have a multiple slave. you will close one channel then open another. 

    2. using 3 pin mode.   config eg: D12  (SPI0_CS0)  AS ping mux 7,  treated like a GPIO.  it will become gpio_42.

    disadvnatech: timing is very hard to control, if you want  "latch enable time" within 10 nano second, it is a scrwed up.   however, if you want  "latch enable time" more than x nano second. there is no problem.

    Hi,  :

    maybe it is not direct support.
    It is definitely supported otherway. am64x, chip is very powerful, please read the source code as well as schematics. 

    Thanks.

  • 0 in reply to Jun Tu
    TI__Guru**** 166599 points

    Hello Jun Tu,

    Thank you.

    The expert mentioned we currently do not support SPI slave,

    Jun Tu said:
    It is definitely supported otherway. am64x, chip is very powerful, please read the source code as well as schematics. 

    You mentioned hardware - could you please elaborate.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Expert 1320 points

    I mean:

    "TI supports the 'latch enable' function for SPI in both master and slave modes, but it requires configuration. For example, you can use a GPIO pin, set to pinmux 7, and manually toggle it high or low in any desired pattern. This setup allows for software-controlled GPIO toggling."

  • 0 in reply to Jun Tu
    TI__Guru**** 166599 points

    Hello Jun Tu,

    Thank you.

    Regards,

    Sreenivasa