C6713B PLLCSR register bit 5:4 Reserved Bit will changel.

That reserved bit is related to the PLL losing its lock, i.e. it's a status bit.  If the PLL is losing lock then something in your system is out of spec, e.g. input clock frequency, intermediate PLL output, divider ratios, etc.  Please read VERY carefully through the data sheet to figure out where things have gone wrong in your system.  Once you figure out what spec in the data sheet you have violated then your PLL will stay locked and PLLCSR won't change.

Dear Brad,

Many Thanks for your help and comment.

We follow SPRU233C.pdf and carefully to config PLL setting as below:

PLLREF=25MHz
PLLOUT=575Mhz
SYSCLK1=191.6MHz
SYSCLK2=95.8MHz
SYSCLK3=95.8MHz

To initialztion PLL Mode and modify the code as below, and it will have the same issue if we power off/on several times then it will happen and SYSCLK3 output will change to 33.3MHz . Could you help to watch the code , Is something wrong ? We are wondering why the clock will change ? Thanks your help.

;************************************************************************
;* CONFIGURE PLL
;************************************************************************
    .IF     INIT_REG_PLL

                        mvkl PLL_CSR,A4
                        mvkl 000000000h,B4
                        mvkh PLL_CSR,A4
                        mvkh 000000000h,B4
                        stw B4,*A4   ;BIT0 0:Bypass mode.
;(1)In PLLCSR,write PLLEN=0(bypass mode)

                        nop 4
;(2)wait 4 cycle of the solowest of PLLOUT

                        mvkl PLL_CSR,A4
                        mvkl 000000008h,B4
                        mvkh PLL_CSR,A4
                        mvkh 000000008h,B4
                        stw B4,*A4   ;BIT3 1:PLL reset is asserted
;(3)In PLL CSR,write PLLRST=1


                        mvkl PLL_DIV0,A4
                        mvkl 000008000h,B4 ;DnEN,Divider=1 25M
                        mvkh PLL_DIV0,A4
                        mvkh 000008000h,B4
                        stw B4,*A4

                        mvkl PLL_M,A4
                        mvkl 000000017h,B4 ;25M*24=600M
                        mvkh PLL_M,A4
                        mvkh 000000017h,B4
                        stw B4,*A4

                        mvkl PLL_OSCDIV1,A4
                        mvkl 000008000h,B4 ;DnEN,Divider=1 25M
                        mvkh PLL_OSCDIV1,A4
                        mvkh 000008000h,B4
                        stw B4,*A4
;(4)Program PLLDIV0,PLLM,OSCDIV1

                        mvkl PLL_DIV1,A4
                        mvkl 000008002h,B4 ;DnEN,Divider=3 600M/3=200
                        mvkh PLL_DIV1,A4
                        mvkh 000008002h,B4
                        stw B4,*A4
                        nop 8 ;mube be wait states between access to PLLDIV1-3

                        mvkl PLL_DIV2,A4
                        mvkl 000008005h,B4 ;DnEN,Divider=6 600M/6=100
                        mvkh PLL_DIV2,A4
                        mvkh 000008005h,B4
                        stw B4,*A4
                        nop 8 ;mube be wait states between access to PLLDIV1-3
                       
                        mvkl PLL_DIV3,A4
                        mvkl 000008005h,B4 ;DnEN,Divider=6 600M/6=100
                        mvkh PLL_DIV3,A4
                        mvkh 000008005h,B4
                        stw B4,*A4
                        nop 8 ;mube be wait states between access to PLLDIV1-3
                       
;(5)Program PLLDIV 1-3

                        nop 4 ;//40ns *4=160ns (reset time MIN 125ns)
;(6)Wait for pLL to Properly reset

                        mvkl PLL_CSR,A4
                        mvkl 000000000h,B4
                        mvkh PLL_CSR,A4
                        mvkh 000000000h,B4
                        stw B4,*A4   ;BIT3 1:PLL reset is released

;(7)Write PLLRST=0 to bring PLL out of reset

                        mvkl 000000209h,A1 ;521
                        mvkh 000000209h,A1
_Lockloop:        
                        sub  A1,1,A1
                        nop 9
                  [A1]  B _Lockloop

;(8)Wait PLL to Lock  521*9*40=187.56us

                        mvkl PLL_CSR,A4
                        mvkl 000000001h,B4
                        mvkh PLL_CSR,A4
                        mvkh 000000001h,B4
                        stw B4,*A4;BIT0 1:PLL mode.

;(9)In PLLCSR,write PLLEN=1 to enable PLL mode

    .ENDIF

no5870 said:

                        mvkl PLL_DIV1,A4
                        mvkl 000008002h,B4 ;DnEN,Divider=3 600M/3=200
                        mvkh PLL_DIV1,A4
                        mvkh 000008002h,B4
                        stw B4,*A4
                        nop 8 ;mube be wait states between access to PLLDIV1-3

                        mvkl PLL_DIV2,A4
                        mvkl 000008005h,B4 ;DnEN,Divider=6 600M/6=100
                        mvkh PLL_DIV2,A4
                        mvkh 000008005h,B4
                        stw B4,*A4
                        nop 8 ;mube be wait states between access to PLLDIV1-3
                       
                        mvkl PLL_DIV3,A4
                        mvkl 000008005h,B4 ;DnEN,Divider=6 600M/6=100
                        mvkh PLL_DIV3,A4
                        mvkh 000008005h,B4
                        stw B4,*A4
                        nop 8 ;mube be wait states between access to PLLDIV1-3
                       
;(5)Program PLLDIV 1-3

This code violates the data sheet.  Specifically, after you've programmed PLL_DIV1 but before programming PLL_DIV2 you will have the following clock frequencies:

• SYSCLK1 = 200 MHz
• SYSCLK2 = 300 MHz (default divider is /2)

This violates the following from the data sheet:

During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output
clocks, see Figure 15), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to
ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower.

The solution is to simply program PLL_DIV2 first and then program PLL_DIV1.  That way SYSCLK2 always remains <= SYSCLK1 / 2.

I try the method which uses you to provide, but PLL lock error still exists.

When PLL lock error I try reset PLL register as below:

Divider D0=0x0000

Divider D1=0x0000

Divider D2=0x0001

Divider D3=0x0001

PLLM=0x0007

I can get ECLKOUT=100M Hz..

But I don’t understand what factors will make PLL lock error.

Do you have the recommended EMI filter and capacitors on the PLLHV pin?  How does your input clock look, i.e. are the transitions <=5ns?