TMDS64EVM: Detect CPU clock fault?

Hello Jakub,

I assume you are using Linux on the A53 cores, and you are asking about detecting frequency fluctuations in the A53 cores specifically?

Please note that PLL instability was possible on earlier versions of the Linux SDK. SDK 10.0 is released with updated firmware that fixes the PLL instability. For more information, look here: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/10_00_07_04/exports/docs/devices/AM64X/linux/Release_Specific_Migration_Guide.html?highlight=pll

Regards,

Nick

Hello Nick

Yes, exactly A53. Sorry for not adding more comprehensive description of the topic. Good to here that PLL initialization procedure was improved in SDK10. Anyway, in our product based on AM6442 cpu we need to detect situation in which in some conditions cpu clock may work incorrectly and take some actions like switching relays and reporting error. So is it exists some API that could help to achieve that goal from user space application level?

I noticed in datasheet there is The Dual Clock Comparator (DCC) module for that purpose. I also found some example code in sdk for R5 core, but didn't found anything for A53 core. Can you provide such an example?

Hello Jakub,

It looks like we do not provide DCC support for Linux on AM64x. Please refer to the SW Build sheet:
https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_00_00_20/exports/docs/build_sheet/am64x-sw-buildsheet.html 

I double-checked in the Linux devicetree, and I did not see anything that looked like the dual clock comparator.

arch/arm64/boot/dts/ti$ grep -r --include=k3-am64* dcc
arch/arm64/boot/dts/ti$ grep -r --include=k3-am64* dual
arch/arm64/boot/dts/ti$ grep -r --include=k3-am64* clock

Can you tell us a bit more about these conditions that you are worried about?

For example, if the system time in the AM64x needs to stay aligned with an external clock source, I usually see customers implement something like PTP over Ethernet in order to make sure the clocks are aligned.

Regards,

Nick

Nick: please request DCC support in the Linux SDKs v10.2 for AM6x; I could foresee this as a potential problem with applications with multiple Ethernet domains off of an A53 core (please cc:  (+) Daolin Qiu's Profile - Daolin Qiu - TI E2E support forums  on this )

thanks, Jim

Hello Jim,

Can you be a bit more explicit with where you foresee potential problems?

Regards,

Nick

Hi Nick,

After few consultations in a team we decide to implement our functionality on R5 core side, no A53. We want in our device have some kind of supervisor which will be monitor different subsystems of the device including CPU clock. Anyway I have and issue with compiling the code on R5 which use this API
First I checked this example It compiles fine. I checked sysconfig of this example project but I didn't found anything related to DCC. I have included header files <sdl/dcc/v0/sdl_dcc.h>  and <sdl/sdl_dcc.h>. Could you tell how to make this API be visible to the linker?
The linker complains:

Hello Jakub,

Understood. I am reassigning your thread to a team member who is more familiar with the MCU+ SDK. This is a holiday week in India, so expect responses to be delayed. Feel free to ping the thread if you do not get a response within a few business days.

Regards,

Nick

Hello Nick,

I just want to add that we are using mcu+sdk in version 9.00.00.35. As of now, we don't plan to migrate to the newest one. Is this DCC functionality should be also proviede by SDK 9.00?

Syscfg of our application:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM64x" --part "Default" --package "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@09.00.00"
 * @v2CliArgs --device "AM6442" --package "FCBGA (ALV)" --variant "AM6442-D" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@09.00.00"
 * @versions {"tool":"1.21.0+3721"}
 */

/**
 * Import the modules used in this configuration.
 */
const epwm       = scripting.addModule("/drivers/epwm/epwm", {}, false);
const epwm1      = epwm.addInstance();
const esm        = scripting.addModule("/drivers/esm/esm", {}, false);
const esm1       = esm.addInstance();
const gpio       = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1      = gpio.addInstance();
const gpio2      = gpio.addInstance();
const gpio3      = gpio.addInstance();
const gpio4      = gpio.addInstance();
const gpio5      = gpio.addInstance();
const gpio6      = gpio.addInstance();
const gpio7      = gpio.addInstance();
const gpio8      = gpio.addInstance();
const gpio9      = gpio.addInstance();
const i2c        = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1       = i2c.addInstance();
const ipc        = scripting.addModule("/drivers/ipc/ipc");
const mcspi      = scripting.addModule("/drivers/mcspi/mcspi", {}, false);
const mcspi1     = mcspi.addInstance();
const udma       = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1      = udma.addInstance();
const watchdog   = scripting.addModule("/drivers/watchdog/watchdog", {}, false);
const watchdog1  = watchdog.addInstance();
const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const mpu_armv77 = mpu_armv7.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
epwm1.$name            = "ADC_MCLK_EPWM4";
epwm1.EPWM.$assign     = "EHRPWM4";
epwm1.EPWM.A.$assign   = "GPMC0_OEn_REn";
epwm1.EPWM.B.$used     = false;
epwm1.EPWM.SYNCO.$used = false;
epwm1.EPWM.SYNCI.rx    = false;
epwm1.EPWM.SYNCI.$used = false;

esm1.$name                      = "CONFIG_ESM0";
esm1.esmNotifier[0].$name       = "CONFIG_ESM_NOTIFY0";
esm1.esmNotifier[0].errorNumber = 162;
esm1.esmNotifier[0].notify      = "ESM_Callback";

gpio1.$name                = "ADC_DRDY";
gpio1.trigType             = "RISE_EDGE";
gpio1.GPIO.gpioPin.pu_pd   = "pd";
gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn0";

gpio2.$name                = "ADC_CONVST_SAR";
gpio2.pinDir               = "OUTPUT";
gpio2.GPIO.gpioPin.pu_pd   = "pu";
gpio2.GPIO.gpioPin.rx      = false;
gpio2.GPIO.gpioPin.$assign = "GPMC0_BE0n_CLE";

gpio3.$name                = "ADC_START";
gpio3.pinDir               = "OUTPUT";
gpio3.GPIO.gpioPin.pu_pd   = "pd";
gpio3.GPIO.gpioPin.rx      = false;
gpio3.GPIO.gpioPin.$assign = "GPMC0_BE1n";

gpio4.$name                = "ADC_ALERT_IRQ";
gpio4.trigType             = "FALL_EDGE";
gpio4.GPIO.$assign         = "GPIO0";
gpio4.GPIO.gpioPin.pu_pd   = "pd";
gpio4.GPIO.gpioPin.$assign = "GPMC0_WAIT1";

gpio5.$name                = "ADC_SYNC_TEST_OUT";
gpio5.pinDir               = "OUTPUT";
gpio5.GPIO.gpioPin.rx      = false;
gpio5.GPIO.gpioPin.$assign = "GPMC0_WPn";

gpio6.$name                = "PRU_PPS_IRQ";
gpio6.trigType             = "RISE_EDGE";
gpio6.GPIO.$assign         = "GPIO0";
gpio6.GPIO.gpioPin.pu_pd   = "pd";
gpio6.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO3";

gpio7.$name                = "BIO_INT_A";
gpio7.trigType             = "FALL_EDGE";
gpio7.GPIO.$assign         = "GPIO0";
gpio7.GPIO.gpioPin.pu_pd   = "pu";
gpio7.GPIO.gpioPin.$assign = "GPMC0_WAIT0";

gpio8.$name                = "BIO_INT3";
gpio8.trigType             = "FALL_EDGE";
gpio8.GPIO.$assign         = "GPIO0";
gpio8.GPIO.gpioPin.pu_pd   = "pu";
gpio8.GPIO.gpioPin.$assign = "OSPI0_CSn3";

gpio9.$name                = "RTC_PPS_IRQ";
gpio9.trigType             = "RISE_EDGE";
gpio9.GPIO.$assign         = "GPIO0";
gpio9.GPIO.gpioPin.$assign = "GPMC0_CSn2";

i2c1.$name       = "MEAS_CARD_I2C1";
i2c1.I2C.$assign = "I2C1";

ipc.enableLinuxIpc = true;
ipc.r5fss0_1       = "NONE";
ipc.r5fss1_0       = "NONE";
ipc.r5fss1_1       = "NONE";
ipc.m4fss0_0       = "NONE";

mcspi1.$name                       = "CONFIG_MCSPI0";
mcspi1.intrEnable                  = "DMA";
mcspi1.intrPriority                = 2;
mcspi1.transferMode                = "CALLBACK";
mcspi1.transferCallbackFxn         = "MCSPI0_TransferCallback";
mcspi1.advanced                    = true;
mcspi1.mcspiChannel[0].$name       = "CONFIG_MCSPI_CH0";
mcspi1.mcspiChannel[0].bitRate     = 15000000;
mcspi1.mcspiChannel[0].frameFormat = "POL0_PHA1";

udma1.$name       = "CONFIG_UDMA0";
mcspi1.udmaDriver = udma1;

watchdog1.$name          = "CONFIG_WDT0";
watchdog1.expirationTime = 45000;
watchdog1.resetMode      = "Watchdog_RESET_OFF";
watchdog1.instance       = "WDT8";

debug_log.enableCssLog = false;

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x41010000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv75.$name    = "CONFIG_MPU_REGION5";
mpu_armv75.baseAddr = 0x80000000;
mpu_armv75.size     = 31;

mpu_armv76.$name        = "TCMB_R5F";
mpu_armv76.attributes   = "NonCached";
mpu_armv76.allowExecute = false;
mpu_armv76.size         = 15;
mpu_armv76.baseAddr     = 0x41010000;

mpu_armv77.$name        = "CONFIG_MPU_REGION6";
mpu_armv77.size         = 20;
mpu_armv77.baseAddr     = 0xA0000000;
mpu_armv77.attributes   = "NonCached";
mpu_armv77.allowExecute = false;

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
gpio1.GPIO.$suggestSolution                 = "GPIO0";
gpio2.GPIO.$suggestSolution                 = "GPIO0";
gpio3.GPIO.$suggestSolution                 = "GPIO0";
gpio5.GPIO.$suggestSolution                 = "GPIO0";
i2c1.I2C.SCL.$suggestSolution               = "I2C1_SCL";
i2c1.I2C.SDA.$suggestSolution               = "I2C1_SDA";
mcspi1.SPI.$suggestSolution                 = "SPI0";
mcspi1.SPI.CLK.$suggestSolution             = "SPI0_CLK";
mcspi1.SPI.D0.$suggestSolution              = "SPI0_D0";
mcspi1.SPI.D1.$suggestSolution              = "SPI0_D1";
mcspi1.mcspiChannel[0].CSn.$suggestSolution = "SPI0_CS0";

BR,

Jakub

Hello Jakub,

Apologies for the delay here.

Yes, DCC is also supported in 9.0 MCU+SDK. The DCC initialisation is directly done in the application itself and hence you do not see it present in the syscfg tool. 

You can go through the DCC example present and let me know if you have any additional questions on DCC configuration etc. 

(mcu_plus_sdk_am64x_09_00_00_35/examples/sdl/dcc/dcc_modes)

Regards,

Nihar Potturu. 

Hello Nihar,

Thanks for response. For now I have code with initialized and running DCC peripheral. Now I want to test it by dynamically changing clock source frequency and see if error interrupt is triggered. For that purpose I have used k3conf tool by typing command: k3conf set clock 16 6 25000000 which should change clock source 6 frequency to desired. But nothing actually happens...

root@puma:~# k3conf set clock 16 6 25000000
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-88-g982f5c2 built Mon Nov 4 11:02:54 AM UTC 2024) |
| SoC | AM64x SR2.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') |
|--------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|-------------------------------------------------------------------------------------|
| 16 | 0 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 |
| 16 | 1 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 80000000 |
| 16 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 |
| 16 | 3 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 250000000 |
| 16 | 4 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 25000000 |
| 16 | 5 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 |
| 16 | 6 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 |
| 16 | 7 | DEV_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 60000000 |
| 16 | 8 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 25000000 |
| 16 | 9 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 |
| 16 | 10 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 |
| 16 | 11 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 |
| 16 | 12 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 |
|-------------------------------------------------------------------------------------|

DEV_DCC0_DCC_CLKSRC6_CLK still have 500 MHz frequency. Can you please elaborate how this tool should be used?

As of know the only way that brings to my mind to check if my DCC code work fine is to intentionally initialize CLK_SRC timer counts into wrong value, to trigger ESM error interrupt (I mean DCC0_INTR_ERR_LEVEL_0 (112) form reference manual page: 5829). But in that case board reset almost immediately after application start. So is it default behaviour that ESM reset SoC when interrupt was fired? Can I detect somehow the root cause of reboot after by reading some persistent register or something?

Also I noticed one more issue:

TRM states that to enable clock source 0/1 the KEY bits need to be set:

I noticed that even if SDL_DCC_Configure set those bits to the correct pattern they are still unset. I also tried to set them manually, but they are still unset...
Here is output form my test application and also source code (note the register offset 0x24 and 0x28)

void DCC0_IntrErrHandler(void *arg)
{
    SDL_DCC_clearIntr(SDL_DCC_INST_DCC0, SDL_DCC_INTERRUPT_ERR);
    SetFault(SYSCLK_CLOCK_FAULT);
    assert(0);
}

static void DCCPrintRegisters(SDL_DCC_Inst instance)
{
    DebugP_log("DCC%d register map:\r\n",instance);
    uint32_t dccBaseAddr = 0;
    if(SDL_PASS == SDL_DCC_getBaseaddr((SDL_DCC_Inst)instance, &dccBaseAddr))
    {
         for(int i=0; i<=SDL_DCC2_DCCERRCNT; i+=4) 
         {
            uint32_t regValue = HW_RD_REG32(dccBaseAddr + i);
            DebugP_log("DCC%d reg: %#lx (offset: %#x) | value: %#lx\r\n",instance,(long unsigned int)dccBaseAddr+i,i,(long unsigned int)regValue);
         }
    }   
}

static int32_t EnableErrorInterrupt(SDL_DCC_Inst instance)
{
    int32_t ret = SDL_PASS;

    DebugP_log("ESM Error interrupt %d registration for DCC%d\r\n",TestClockLookupTable[instance].intNum,instance);

    SDL_DPL_HwipParams intrParams = {
        .intNum      = TestClockLookupTable[instance].intNum,
        .callback    = &DCC0_IntrErrHandler,
        .callbackArg = (uintptr_t)&instance
    };

    if((ret = SDL_DPL_registerInterrupt(&intrParams,&TestClockLookupTable[instance].intrHandle)) != SDL_PASS)
    {
        DebugP_log("ESM interrupt registration for DCC%d failed! Error: %#x\r\n",instance,ret);
        return ret;
    }

    if((ret = SDL_DCC_enableIntr(instance, SDL_DCC_INTERRUPT_ERR)) != SDL_PASS)
    {
        DebugP_log("DCC%d enable interrupt fail! Error: %#x\r\n",instance,ret);
    }

    return ret;
}


static int32_t DCCInstanceInit(SDL_DCC_Inst instance, ClockName clockName, double freqDrifftRatio) {

    if(instance > SDL_DCC_INST_DCC5)
    {
        DebugP_log("DCC%d is incorrect instance for main domain!\r\n", instance);
        return SDL_EINVALID_PARAMS;
    }

    int32_t ret = SDL_PASS;
    SDL_DCC_Config config;
    memset(&config,0,sizeof(SDL_DCC_Config));

    TestClockInfo * clockInfo = ClockInfoLookup(instance,clockName);

    if(!clockInfo)
    {
        DebugP_log("Clock info not found for DCC%d instance\r\n", instance);
        return SDL_EBADARGS;
    }

    SetReferenceClockSource(&config);
    SetTargetClockSource(&config,clockInfo->source);
    SetDCCContinousMode(&config);

    if((ret = CalculateCounters(&config,freqDrifftRatio,REF_CLOCK_RC_OSC_HZ,clockInfo->freqHz)) != SDL_PASS)
    {
        return ret;
    }

    DebugP_log("DCC%d config summary:\r\n",instance);
    DebugP_log("\tDCC mode:\r\n",config.mode);
    DebugP_log("\tDCC Clock Source 0 id: %d\r\n",config.clk0Src);
    DebugP_log("\tDCC Clock Source 1 id: %d\r\n",config.clk1Src);
    DebugP_log("\tDCC Clock Source 0 seed: %ld\r\n",config.clk0Seed);
    DebugP_log("\tDCC Clock Source 1 seed: %ld\r\n",config.clk1Seed);
    DebugP_log("\tDCC Valid window seed: %ld\r\n",config.clk0ValidSeed);


    uint32_t dccBaseAddr = 0;
    if(SDL_PASS == SDL_DCC_getBaseaddr((SDL_DCC_Inst)instance, &dccBaseAddr))
    {
        //Continues to next window of comparison despite the error condition.
        HW_WR_FIELD32(dccBaseAddr + SDL_DCC2_DCCGCTRL2,SDL_DCC2_DCCGCTRL2_CONT_ON_ERR,0xFF);
    }

    if((ret = SDL_DCC_configure(instance,&config)) != SDL_PASS)
    {
        DebugP_log("DCC%d configuration failed! Error: %#x\r\n",instance,ret);
        return ret;
    }
    
    if((ret = SDL_DCC_verifyConfig(instance, &config)) != SDL_PASS)
    {
        DebugP_log("DCC%d configuration verification failed! Error: %#x\r\n",instance,ret);
        return ret;
    }

    if((ret = EnableErrorInterrupt(instance)) != SDL_PASS)
    {
        DebugP_log("DCC%d interrupt configuration failed! Error: %#x\r\n",instance,ret);
        return ret;
    }

    DebugP_log("DCC configuration result: %#x\r\n",ret);

    ret = SDL_DCC_enable(instance);

    if(dccBaseAddr)
    {
        /* Enable clock source selection for COUNT0 */
        HW_WR_FIELD32(dccBaseAddr + SDL_DCC2_DCCCLKSRC0,SDL_DCC2_DCCCLKSRC0_KEY,SDL_DCC2_DCCCLKSRC0_KEY_ENABLE);
        /* Enable clock source selection for COUNT1 */
        HW_WR_FIELD32(dccBaseAddr + SDL_DCC2_DCCCLKSRC1,SDL_DCC2_DCCCLKSRC1_KEY,SDL_DCC2_DCCCLKSRC1_KEY_ENABLE);
    }

    DCCPrintRegisters(instance);

    return ret;
}

Hello Jakub,,

I am going through the other points you shared. Please give me a couple of days to respond on them.

Jakub Grad said:

Can I detect somehow the root cause of reboot after by reading some persistent register or something?

You can use the RST_SRC register to get the reset reason.

Regards,

Nihar Potturu. 

Hello Nihar

Thanks for response. Regarding to KEY bits in registers 0x24/0x28 this is not explicitly mentioned in TRM but I think they are only required to change clock source and then they cleared - it is something like fuse against accidently misconfiguring something. Anyway my code works. I found that board rebooting is related to the priority of ESM interrupt. If it is high, then board is immediately rebooted in case of interrupt appear. I tested the solution by intentionally program DCC Counter 1 to incorrect value regarding to current clock frequency to see if error interrupt occurs - it does. But I would rather have a possibility to dynamically change frequency of the clock using k3conf tool by calling command k3conf set clock 16 6 25000000. As I mentioned earlier this command does not work, the clock frequency stays the same. Can you provide me a support in this matter? I don't know if I should create another topic for that or shall we continue here?