Tool/software:
Hello experts!!
I've experienced some weird behaviour and I would like to ask you any kind of hint of where to look.
I had a buffer on DDR memory that was written by the A15(Linux) and read asynchronously by the C66x (TI-RTOS). Most of the times the data read by the C66x was right, but sometimes (if the C66x read the buffer short after it was written by the A15) it happenned to have wrong data. I've seen it completely corrupt, partially corrupt (size of the corrupted part multiple of 16 bytes) or right.
We implemented a notification from the C66x to IPU1 (TI-RTOS) to check the same memory address the C66x was reading and we found that the IPU1 was seeing the data as wrong as the C66x, but if we asked the IPU1 to read the same memory positions again some seconds later, it appeared to be right.
We thought it could be some kind of issue with the DMA so we added a sanity signature right after and before the buffer (both written/updated with new values by the A15 every time the buffer was read, a not elaborated hash) and we saw that most of the times both signatures were OK, sometimes one of the signatures was not properly updated and in rare cases none of the signatures.
We thought too that the memory could be cached on Linux-A15 side but it seems that /dev/mem (used with mmap) is not cached. Is this true or is there any kind of caché on /dev/mem?
Both C66x (MAR registers) and IPU1 (AMMU) don't cache the memory area where the buffer is located.
So, the final somersault was to move the buffer from DDR to OCMC and it works perfectly!
Would you be so kind to tell me anything that I could check/investigate to understand why it works on OCMC but not on DDR? Any baseline? Any idea? Caché? DMA? Other? Which differences between EMIF-DDR and OCMC should I focus at?
Thank you ind advanced for any help!
