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TMS320VC5507: Power down sequence

satoshi shimose
Prodigy 40 points
Part Number: TMS320VC5507

Tool/software:

Hi supporting team,

I have a question about power-down control. The TMS320VC5507 specifications do not require power-down control. Is there anything I should be careful about regarding DVDD and CVDD voltage control? In our application, an unexpected signal is being output from the I2C port while the DVDD (3.3V) and CVDD (1.2) voltages are dropping, and we are investigating the cause. CVDD is falling behind DVDD, and we suspect that this may be the problem.

Thanks and Best Regards,

I2Cunknown.pdf

  • 0
    TI__Prodigy 270 points

    Hi, 

    Thanks for your question. As you mentioned, the order of power-down of CVDD and DVDD don't matter as there is no power-down sequence. As they are powering down, what is the state of ~Reset while this power-down is happening? I suspect your ~Reset may still be high while CVDD and DVDD are powering down which will explain the unexpected behavior of the I2C SDA, as CVDD and DVDD voltages drop well below the recommended operation conditions as seen on the pdf you provided (DVDD-1.4V and CVDD-0.8V). 

  • 0 in reply to Fabrice Nguegang
    Prodigy 40 points

    Hi Nguegang,

    Thanks for your answer.

    I checked the falling edge of the RESET inverting terminal. It appears to be synchronized with Vcc, and when the unexpected behavior occurs it is around 1.5V. The IC specification sheet do not seem to specify how the RESET inverting terminal should behave during power-down. But does this mean that in order for the IC to operate normally, RESET inverting needs to fall before DVDD and CVDD?

    Thanks and Best Regards,

    RESET terminal.pdf

  • +1 in reply to satoshi shimose
    TI__Prodigy 270 points

    Hi Shimose,

    Thanks for your swift response, 

    Yes, for the IC to operate normally, RESET needs to fall before DVDD and CVDD. on the image you provided, it seems that RESET is not yet below 2V which is the minimum input voltage at which RESET is guaranteed to be read as a logic high (As seen on page 75 of the datasheet). Because DVDD is sync'd with RESET, RESET is still going to be read as a logic high by the time both RESET and DVDD drop below DVDD's minimum recommended operating level of 2.7V. This range of uncertainty is going to continue until RESET drops to a level below 0.8V, which is the maximum voltage at which RESET is guaranteed to be read as a logic LOW. That should explain why you are seeing unexpected behavior.

  • 0 in reply to Fabrice Nguegang
    Prodigy 40 points

    Hi Nguegang,

    Thanks for your answer.

    We will take measures based on that information.

    Thanks and Best Regards,