DM368 with DDR2 memory

More specifically, I believe what the customer is concerned with is the following:

Table 4 of http://download.micron.com/pdf/technotes/ddr2/TN4716.pdf   indicates for the "IT" version of the Micron SDRAM, the refresh rate has to be 3.9 us.  This is also suppported in the micron datasheet http://www.micron.com/get-document/?documentId=456&file=1GbDDR2.pdf on page 10 at the bottom "Industrial Temperature" where it is indicated the refresh rate has to be doubled as well on on Page 39 - Table 12 where the parameter tREFIIT is shown as 3.9us for the "IT" parts. 

So the question is "Can the DM368 DRAM controller be configured to support this refresh rate for industrial temp parts?"

I have done some more work on this and think I may have found the answer.  So, I need confirmation this will work:

Based on reading the top of page 43 of App Note SPRUFI2 (March 2009) , there is an example of how to set the Refresh Rate based on a 7.8us refresh.  On this page, Table 17 is supposed to be the information from the DDR2 datasheet.  So, if one runs the equation just below Table 17 using the new refresh rate numbers and clock frequency, it should produce a new value for the SDRCR register.

The example is:

RR = 133 MHz ´ 7.8 ms = 1037.4

Therefore, RR = 1038 = 40Eh.

The new values would be:

RR = 333 MHz ´ 3.9 ms = 1298.7

Therefore, RR = 1299 = 513h.

Is this new refresh rate a valid setting for a 3.9us refresh?

Yes the RR supports up to FFFFh, so I'm not sure why the customer is claiming that our controller cannot support a 3.9ms rate.

Jeff

I think the refresh register setting has been put to rest.  The other issue the customer was concerned about is the Trasmax setting.  It can also be set to a max of Fh.  He was concerned the micron datasheet indicated a trasmax of 70,000ns.  However, the max setting on the DM368 of Fh gives a setting in 64,400ns which I think is OK because it is less than the max in the micron datasheet (40ns min - 70,000ns max).

Hi Guys,

We still have problem with bringing up our HW (based mostly on the Leopard).

We have DDR2 memeory but IT version. (MT47H64M16HR-25E:IT)

Our config in UBL is following :

// INDUSTRIAL MEM
static const Uint16 DDR_T_RFC = 1275;         //default 127.5us (1275)
static const Uint16 DDR_T_RP = 125;           //default 20us (200) -> 12.5us (125)
static const Uint16 DDR_T_RCD = 125;          // 200 -> 125
static const Uint16 DDR_T_WR = 150 ;          // OK
static const Uint16 DDR_T_RAS = 450;          // 40-70.. OK ns
static const Uint16 DDR_T_RC = 550;          // default-650, -> 550
static const Uint16 DDR_T_RRD = 100;          // default 100 -> MIN 75 OK
static const Uint16 DDR_T_WTR = 100;          // default 100 -> MIN 75 OK
static const Uint32 DDR_T_RASMAX = 700000;     // OK TRAS MAX 70k
static const Uint16 DDR_T_XP = 2;            // MIN = 2 OK
static const Uint16 DDR_T_XSNR = 1375;      // min = T_RFC + 10ns OK
static const Uint16 DDR_T_XSRD = 200;        // default = 199 -> MIN = 200
static const Uint16 DDR_T_RTP = 75;            // OK
static const Uint16 DDR_T_CKE = 3;            // OK min = 3
static const Uint16 DDR_RR = 39;             // was 7,8us (78) , is 3.9 (39)

Could somone check if above parameters are correct?

Thanks in advance for any suggestions.

Rgds,

Mariusz

        Hi Mariusz Osowski,

    I've got the same problem as you.
    I am currently developing a board with the DM368 and RAM MT47H64M16HR-25E IT:H. I use a copy of the SD Card DM368 EVM SDK where there is 3 partitions (BOOT START_HERE ROOTFS). The uboot and linuxSDK are in the SD CARD .
    I've got my personnal board and I want to change de timing DDR for this I've got to modify the file
/ti-dvsdk_dm368-evm_4_02_00_06/psp/flash-utils/DM36x/Common/src/device.c.

My parameters are:
static const Uint16 DDR_T_RFC = 1275;
static const Uint16 DDR_T_RP = 125;
static const Uint16 DDR_T_RCD = 125;
static const Uint16 DDR_T_WR = 150 ;
static const Uint16 DDR_T_RAS = 400;
static const Uint16 DDR_T_RC = 550;
static const Uint16 DDR_T_RRD = 100;
static const Uint16 DDR_T_WTR = 75;
static const Uint32 DDR_T_RASMAX = 700000;
static const Uint16 DDR_T_XP = 2;
static const Uint16 DDR_T_XSNR = 1375;
static const Uint16 DDR_T_XSRD = 200;
static const Uint16 DDR_T_RTP = 75;
static const Uint16 DDR_T_CKE = 3;
static const Uint16 DDR_RR = 78;I've got modify the variable too

after that I make an make linux_clean ==> make linux ==> make linux install
Do you thinks it's the good way to compile and install and boot on SD CARD.

(In Rules.make : EXEC_DIR=/media/ROOTFS (SD partition ROOTFS)).

Thanks

Maxime Suire

Hi Maxime,

> Do you thinks it's the good way to compile and install and boot on SD CARD.

It is depend what you want to do.

On the one hand you have OS and 'user data' in one place. On the other hand - if SD will be broken your device will not work.

We are using boot from SD card for development porpose only.

Finally our device will boot from NAND and SD card will use as data storage.

Regards,

Mariusz

        Hi Mariusz Osowski,

    Thanks for your reply I'm in the same case as you (developpe on SD Card and after move to NAND).
I've got a question when you've got modified the file device.c, what do you do to loading your modification to your SD card exactly ??
                                                    (make all, make install all, make linux, make u-boot?????)

I really need your answer because I do not know what to do and no one answered me.

Thanks
            Regards


Maxime Suire

Hi Maxime,

Base on information I got from our SW guys we make UBL and UBOOT only for testing.

Next we will make UBL UBOOT and linux to start all system from SD.

Hope this help

Rgds,

Mariusz

        Hi Mariusz,

    Do you think we have to change #define DDR_FREQ and to PLL parameter in file device.c too ?


    Thanks

    Maxime

Maxime,

I think that change DDR freq is not necessary if your HW is correct.

If you are not certain of the HW board - especially DDR2 rouring -  I'd recommend you to set DDR_FREQ lower (i.e. 70MHz) and change if DDR2 works correctly.

Next try to 'speed up' the DDR_FREQ to value reqiered by your system.

Mariusz

Mariusz,

Did the parameters you had post works with your board?

// INDUSTRIAL MEM
static const Uint16 DDR_T_RFC = 1275;         //default 127.5us (1275)
static const Uint16 DDR_T_RP = 125;           //default 20us (200) -> 12.5us (125)
static const Uint16 DDR_T_RCD = 125;          // 200 -> 125
static const Uint16 DDR_T_WR = 150 ;          // OK
static const Uint16 DDR_T_RAS = 450;          // 40-70.. OK ns
static const Uint16 DDR_T_RC = 550;          // default-650, -> 550
static const Uint16 DDR_T_RRD = 100;          // default 100 -> MIN 75 OK
static const Uint16 DDR_T_WTR = 100;          // default 100 -> MIN 75 OK
static const Uint32 DDR_T_RASMAX = 700000;     // OK TRAS MAX 70k
static const Uint16 DDR_T_XP = 2;            // MIN = 2 OK
static const Uint16 DDR_T_XSNR = 1375;      // min = T_RFC + 10ns OK
static const Uint16 DDR_T_XSRD = 200;        // default = 199 -> MIN = 200
static const Uint16 DDR_T_RTP = 75;            // OK
static const Uint16 DDR_T_CKE = 3;            // OK min = 3
static const Uint16 DDR_RR = 39;             // was 7,8us (78) , is 3.9 (39)

Thanks for all

Maxime

Maxime,

Ultimately we left default UBL values:

//DEFAULT MEM

static const Uint16 DDR_T_RFC = 1275;
static const Uint16 DDR_T_RP = 200;
static const Uint16 DDR_T_RCD = 200;
static const Uint16 DDR_T_WR = 150 ;
static const Uint16 DDR_T_RAS = 450;
static const Uint16 DDR_T_RC = 650;
static const Uint16 DDR_T_RRD = 100;
static const Uint16 DDR_T_WTR = 100;
static const Uint32 DDR_T_RASMAX = 700000;
static const Uint16 DDR_T_XP = 2;
static const Uint16 DDR_T_XSNR = 1375;
static const Uint16 DDR_T_XSRD = 199;
static const Uint16 DDR_T_RTP = 75;
static const Uint16 DDR_T_CKE = 3;
static const Uint16 DDR_RR = 78;

Rgds,

Mariusz