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TDA4VM: TDA4VM Rtos 0806: Ethfw Loopbacken test

dongzhang
Intellectual 340 points
Part Number: TDA4VM

Tool/software:

Hi,
 TDA4VM RTOS 0806
    When I set loopbacken true [Set port2 to SGMII], in

void CpswMacPort_initCfg(CpswMacPort_Cfg *macPortCfg)
{
macPortCfg->loopbackEn = true;
macPortCfg->crcType = ENET_CRC_ETHERNET;
macPortCfg->rxMtu = CPSW_MACPORT_RX_MTU_DEFAULT;
macPortCfg->passPriorityTaggedUnchanged = false;
macPortCfg->vlanCfg.portPri = 0U;
macPortCfg->vlanCfg.portCfi = 0U;
macPortCfg->vlanCfg.portVID = 0U;
macPortCfg->txPriorityType = ENET_EGRESS_PRI_TYPE_FIXED;
macPortCfg->sgmiiMode = ENET_MAC_SGMIIMODE_INVALID;
}
my EVM Hw:
    serdes0 lane1 no connect. 

MCU2_0 run success. and register is :
Memory mapped at address 0xffffa2271000.
Read at address 0x0C000210 (0xffffa2271210): 0x00000010
/dev/mem opened.
Memory mapped at address 0xffffbb0f8000.
Read at address 0x0C000214 (0xffffbb0f8214): 0x00000031
my HW:
    serdes0 lane1  no connect.
MCU2_0 run blocked.
log:
[MCU2_0] 16.979613 s: 01:80:c2:00:00:0e
[MCU2_0] 16.979663 s: 01:1b:19:00:00:00
[MCU2_0] 16.979931 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0] 16.990179 s: Mdio_open: MDIO manual mode enabled
stop here......

and register is :
Memory mapped at address 0xffffa2271000.
Read at address 0x0C000210 (0xffffa2271210): 0x00000000
/dev/mem opened.
Memory mapped at address 0xffffbb0f8000.
Read at address 0x0C000214 (0xffffbb0f8214): 0x00000000
When HW reboot , 
Memory mapped at address 0xffffa2271000.
Read at address 0x0C000210 (0xffffa2271210): 0x00000010
/dev/mem opened.
Memory mapped at address 0xffffbb0f8000.
Read at address 0x0C000214 (0xffffbb0f8214): 0x00000038 ,,,some time 3C
used the same SD card and image.
Is there anything that could cause this problem?
thanks
dongzhang
  • 0
    TI__Guru**** 154230 points

    Hi,

    Part of team is on vacation.. Please expect response early next week.

    Best regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Intellectual 340 points

    I find out the dead loop.

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    static int32_t Cpsw_isPortLinkUp(Cpsw_Handle hCpsw,
    Enet_MacPort macPort,
    bool *linked)
    {
    int32_t status = ENET_SOK;
    #if ENET_CFG_IS_ON(CPSW_SGMII)
    EnetPer_Handle hPer = (EnetPer_Handle)hCpsw;
    CSL_Xge_cpsw_ss_sRegs *ssRegs = (CSL_Xge_cpsw_ss_sRegs *)hPer->virtAddr2;
    uint32_t portNum = ENET_MACPORT_NORM(macPort);
    uint32_t portId = ENET_MACPORT_ID(macPort);
    EnetMod_Handle hMacPort = hCpsw->hMacPort[portNum];
    Enet_IoctlPrms prms;
    EnetMacPort_GenericInArgs macPortInArgs;
    EnetMacPort_Interface mii;
    EnetMac_LayerType enetLayer;
    EnetMac_SublayerType enetSublayer;
    bool sgmiiLink;
    uint32_t qsgmiiId;
    ENETTRACE_VAR(portId);
    status = EnetSoc_getMacPortMii(hPer->enetType, hPer->instId, macPort, &mii);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Output log:
    [MCU2_0]     61.143056 s: ZD goto ... func Cpsw_isPortLinkUp macPort 1 ...Cpsw_isPortLinkUp IOCTL done sgmiiLink  0
    [MCU2_0]     61.143127 s: ZD goto ... func Cpsw_isPortLinkUp macPort 1 ...Cpsw_isPortLinkUp IOCTL done sgmiiLink  0
    [MCU2_0]     61.472563 s: ZD goto ... func Cpsw_isPortLinkUp macPort 1 ...Cpsw_isPortLinkUp IOCTL done sgmiiLink  0
    [MCU2_0]     61.472635 s: ZD goto ... func Cpsw_isPortLinkUp macPort 1 ...Cpsw_isPortLinkUp IOCTL done sgmiiLink  0
    ............


    dongzhang

  • 0 in reply to dongzhang
    Intellectual 340 points

    my board other register:

  • 0 in reply to dongzhang
    Intellectual 340 points

    Sorry for that,

    1. I found that our board Del the 100Mhz clock. IC: CDCI6214RGET , Can it be deleted?  What will be the impact? 

    2. And now,  we need use 19.2Mhz clock, but we changed it to 20Mhz,   What will be the impact?  some other module...

    3. And I found that csl_serdes3.c func: CSL_serdesRefclkSel no setting for 20Mhz, Is there have patch for 20Mhz ?

    thanks alot.

    dongzhang

  • 0 in reply to dongzhang
    TI__Guru 50030 points

    Hi, 

    You need to change the boot mode pins for 20MHz.

    Please refer to TRM for boot mode pins settings. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 340 points

    Hi，
    Hardware Assist I have changed the 20Mhz to 19.2 Mhz which is the same as the EVM
    Then I changed:

    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)0;//AUTOX_LUOHUI_SGMII_SEDERS_INSTANCE;
    serdesLane0EnableParams.baseAddr = CSL_SERDES_16G0_BASE;
    serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_19p2M;//CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT;
    serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes = 0x1;
    serdesLane0EnableParams.laneMask = 0x2; // lane1
    serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum = SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;

    serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
    Do I need to modify those places?

    thanks
    dongzhang
  • 0 in reply to dongzhang
    TI__Guru 50030 points

    Hi, 

    dongzhang said:
    serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_19p2M;//CSL_SERDES_REF_CLOCK_100M;

    Ref clock to be 100M not 19.2

    Also, make sure that Serdes0 not configured from u-boot & Linux. 

    Also, make sure that serdes clock configuration with CSL_SERDES_REF_CLOCK_INT with 100M.

    Please refer to board_j721e_evm.c file from ethfw/utils/board/j721e/.

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Intellectual 340 points

    thanks,
    I changed it back
    serdesLane0EnableParams    .refClock = CSL_SERDES_REF_CLOCK_100M;
    So,  now I used TDA4VM EVM, and use 19.2 as SERDES base clock.
    (Use WKUP_OSC0_XI WKUP_OSC0_XO 19.2Mhz)

    and uboot and Linux used default 0806 image. 

    in board_j721e_evm.c  I found this configuration:

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    static void EthFwBoard_configSierra0Clks(void)
    {
    uint32_t moduleId = TISCI_DEV_SERDES_16G0;
    uint32_t clkRateHz = 100000000U;
    uint32_t clkId[] = {
    TISCI_DEV_SERDES_16G0_CORE_REF1_CLK,
    TISCI_DEV_SERDES_16G0_CORE_REF_CLK};
    uint32_t clkParId[] = {
    TISCI_DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK,
    TISCI_DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK};
    uint32_t i;
    int32_t status;
    for (i = 0U; i < ENET_ARRAYSIZE(clkId); i++)
    {
    status = Sciclient_pmSetModuleClkParent(moduleId, clkId[i], clkParId[i], SCICLIENT_SERVICE_WAIT_FOREVER);
    if (status != CSL_PASS)
    {
    appLogPrintf("Failed to reparent clk %u: %d\n", clkId[i], status);
    EnetAppUtils_assert(false);
    }
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    then should I change the val "uint32_t clkParId[]={}" ? What value should it be set to?

    I test val:

    uint32_t clkParId[] = {
    //TISCI_DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK,
    //TISCI_DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK};
    TISCI_DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT,
    TISCI_DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT};

     log.

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    [MCU2_0] 17.961974 s: APP: Syncing with 5 CPUs ... Done !!!
    [MCU2_0] 17.962169 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0] 17.963853 s: REMOTE_SERVICE: register service name [com.ti.remote_service_test]
    [MCU2_0] 17.963928 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0] 17.963969 s: REMOTE_SERVICE: register service name [rtos_test]
    [MCU2_0] 17.964007 s: REMOTE_SERVICE: register service name [com.ti.perf_stats]
    [MCU2_0] 17.964045 s: ETHFW: Init ... !!!
    [MCU2_0] 17.964090 s: ZD goto ... func EthFwBoard_init
    [MCU2_0] 18.001078 s: PMLIBClkRateSet failed for clock Id = 42
    [MCU2_0] 18.001171 s: Assertion @ Line: 190 in enet_apputils_k3.c: false : failed !!!
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    thanks

    dongzhang

  • 0 in reply to dongzhang
    TI__Guru 50030 points

    Hi, 

    If you want to use SerDes with external clock of 19.2M then you need to configure SerDes clock as 19.2M and clock source should not be CSL_SERDES_REF_CLOCK_INT.

    Then above clock configuration would be fine. 

    If you want use SerDes with internal clock you need use 100M and clock same as default  one from ethfw/utils/board/j721e/board_j721e_evm.c.

    Note:

    We haven't tested SerDes with external clock source from TI SDK.

    Also, by default U-boot & Linux configures SerDes0 for PCIe+ QSGMII. 

    Make sure that SerDes0 should not be configured from U-boot & Linux (disable nodes from device tree) when you want to configure and use from RTOS. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 10 points

    Hello, 

    We want to use WKUP_OSC0 as the clock source of Serdes clock PLL. This WKUP_OSC0 is connected to a 19.2M crystal oscillator.
    19.2M, through the path shown in the figure, generates 100MHz, reaches CMN_REFCLK1_INT, and is provided to Serdes.
    Is this OK?

  • +1 in reply to Bo Mu
    TI__Guru 50030 points

    Hi, 

    Bo Mu said:
    We want to use WKUP_OSC0 as the clock source of Serdes clock PLL. This WKUP_OSC0 is connected to a 19.2M crystal oscillator.
    19.2M, through the path shown in the figure, generates 100MHz, reaches CMN_REFCLK1_INT, and is provided to Serdes

    From the above path, it seems SerDes is feed with internal clock. 

    So, you have to use 100MHz clock for SerDes. Use the SerDes configuration and SerDes clock as shared/suggested above. 

    Also, make sure sure that SerDes0 configuration disable from U-boot & Linux. 

    Best Regards, 

    Sudheer