AM5716: Synchronization of PRU PHYs with Clock Input skew of 5ns.

Hello David,

Reassigning to our HW team to comment.

Josue

DAVID SABALESKY said:

Our design has 1x 100b PHY on PRU1, 2x 100b PHY on PRU2, and 2x Gb PHY on GMAC.

Each PRU has two ports. Each port has an independent PHY attached.

Our design is using Ethercat protocol.

Do you need to synchronize all the clock signals for all 5 PHYs?

Do you need to synchronize clock signals for PRU1 with PRU2?

Can you clarify what each of these ports is intended to do? I'm guessing "PRU2" is running EtherCAT slave/subdevice. What are the other three ports intended to do? Assuming they are not directly related to EtherCAT, I don't see why the synchronization would be needed. We do not support EtherCAT slave/subdevice accross multiple ICSS/PRU subsystems, so 2-ports is the maximum.  

PRU1 and PRU2 are EtherCat. The Gb PHY on GMAC is Ethernet. I understand that PRU ICSS is synchronized with both channels. But PRU1 ICSS to PRU ICSS are never synchronized. The PRU subsystems are never synchronized. Is that correct?  Did you see the clock fan out. There are delays in the outputs of the ICs as well as delay from each output set. Are there any strict timing requirements needed between PHYs and PRU subsystems? Team members have brought to my attention that the PHYs both 100b and Gb should be driven from same clock source with little skew. I am uncertain if this is necessary. Please let me know your thoughts. 

The ICSS EtherCAT slave/subdevice only supports 2 external ports. The 3rd port from another ICSS cannot be part of the same EtherCAT LAN. See https://software-dl.ti.com/processor-industrial-sw/esd/docs/indsw/EtherCAT_Slave/01_00_10/PRU_ICSS_EtherCAT.html#introduction . If your third port is on a separate EtherCAT LAN I don't see a need to have them synchronized.

Hi Pekka,

I am the hardware design engineer. Does the 25MHz clock source for each PHY pair on a PRU Unit need to be synchronized?  Does the clock source driving Gb PHYs have to be synchronized, aka driven from a common clock source - fanout?  I am looking at our clock fan out section to be sure we do not violate any timing requirements for each PRU pair or GMAC PHYs. The belief here is that they all need to be synchronized to the clock source to the AM5716, 25MHz, master clock. I do not see any issue with the current Clock Fan Out circuit as long as each respective PRU PHYs are driven from same clock output with max 100-500ps skew, same from the GPHYs. Please let me know if this is correct. There was an issue here in the past that team members said it was necessary to keep all clocks skew low from each other since the DSP is the source for the internal clock source to the PRUs and GMAC sections. Thank you. David