J721EXSOMXEVM: Using Tertiary Bootloader (BootApp) to boot U-Boot

Please be aware, that TI responsible resource is out of office for the rest of this week, a delay in response may occur.

Regards,

kb

Hello Louie,

Louie Kotler said:

However, using U-Boot with the BootApp (Tertiary Bootloader) is not documented.

It is unclear why you want to load U-Boot using BootApp. The BootApp is intended to load all the cores with respective images.  We expect customers to use either the SPL+UBOOT or SBL+BootApp combination.

Thanks.

We need the LPM demo features (like MCU Only mode and switching to ACTIVE mode) as well as U-Boot because we need some U-Boot features that aren't present in the BootApp. Since the LPM demo uses SBL+BootApp, we want to know if it's possible add on U-Boot by doing SBL+BootApp+UBOOT or SBL+BootApp+SPL+UBOOT. Is there any way to achieve this configuration for the boot flow?

Hi Louie,

Thanks for the details. I checked with Gunter, and he shared the exact details.

The boot flow you requested is not a standard support we provided or tested in our TI SDK, and this looks specific to your project as we have not heard this from any other customer. Ideally, We do not expect customers to mix the SPL+UBOOT and SBL+BootApp flow. Also, TI has not tested the requested flow of SBL+BootApp+UBOOT or SBL+BootApp+SPL+UBOOT. 

Though this flow is theoretically doable, we would need time to plan and test it. We suggest you do it yourself and try to get help from Gunter as we wait for our team in India to return from their vacation to support your concerns/issues.

Thanks.

Hello,

Gunter and I attempted to get a working setup ourselves but we were unsuccessful. Now that the team in India has returned from vacation, can we please receive an update from them? Thanks.

Hi all,

After having validated the LPM bootapp flow with booting the Linux kernel successfully, to be more specific, we have tried the following first:

Hi all,

since we were not sure about using the "u-boot" ELF binary as is, we have tried to use u-boot.bin instead and make an appimage.

This was done by modifying the script at ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/constructappimagehlos.sh 

~/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos$ diff -Nurp constructappimageshlos.sh.orig constructappimageshlos.sh
--- constructappimageshlos.sh.orig	2024-10-29 16:55:02.919507804 -0700
+++ constructappimageshlos.sh	2024-10-31 16:29:04.979724428 -0700
@@ -7,7 +7,8 @@
 MY_BOARD=$1
 
 # OS options are: linux or qnx
-OS=qnx
+OS=linux
+TOOLCHAIN_PATH_GCC_ARCH64=/home/gunter/ti/arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-linux-gnu/bin
 
 # Linux-specific paths
 # --------------------
@@ -17,7 +18,7 @@ OS=qnx
 # base-board.dtb (k3-j72*-common-proc-board.dtb), and Image files
 
 # Linux build directory containing all the locally-built Linux-related binaries
-LINUX_BUILD_DIR_PATH=USER_DEFINED_PATH
+LINUX_BUILD_DIR_PATH=/home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/tools/combined_appimage/bin/${MY_BOARD}
 
 # QNX-specific paths
 # ------------------
@@ -40,7 +41,8 @@ PDK_INSTALL_PATH="${SDK_INSTALL_PATH}/pd
 SBL_REPO_PATH="${PDK_INSTALL_PATH}/ti/boot/sbl"
 MULTICORE_APPIMAGE_GEN_TOOL_PATH="${SBL_REPO_PATH}/tools/multicoreImageGen/bin"
 SBL_OUT2RPRC_GEN_TOOL_PATH="${SBL_REPO_PATH}/tools/out2rprc/bin"
-MULTICOREAPP_BIN_PATH=${PWD}/../../binary/bin/${MY_BOARD}
+#MULTICOREAPP_BIN_PATH=${PWD}/../../binary/bin/${MY_BOARD}
+MULTICOREAPP_BIN_PATH=${PDK_INSTALL_PATH}/ti/boot/sbl/tools/combined_appimage/bin/${MY_BOARD}
 
 LDS_PATH=${PWD}/${OS}
 
@@ -48,7 +50,9 @@ LDS_PATH=${PWD}/${OS}
 if [ $OS == "linux" ]; then
     GenFiles=("atf_optee" \
               "tidtb_linux" \
-              "tikernelimage_linux"
+              "tikernelimage_linux" \
+              "tiubootimage_linux" \
+              "tiubootsplimage_linux"
              );
 fi
 if [ $OS == "qnx" ]; then
@@ -73,7 +77,7 @@ for i in "${GenFiles[@]}"
 do
     echo "Generating $i image"
     if [ $OS == "linux" ]; then
-        aarch64-none-linux-gnu-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf
+        ${TOOLCHAIN_PATH_GCC_ARCH64}/aarch64-none-linux-gnu-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf
     fi
     if [ $OS == "qnx" ]; then
         ${TOOLCHAIN_PATH_GCC_ARCH64}/aarch64-unknown-nto-qnx7.0.0-ld -T $LDS_PATH/$i.lds -o $MULTICOREAPP_BIN_PATH/$i.elf

This makes an appimage

Generating tiubootimage_linux image
WARNING: The runtime version supported by this application is unavailable.
Using default runtime: v4.0.30319
Parsing the input object file, /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/../../../../../../pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/tools/combined_appimage/bin/j721e_evm_lastmile/tiubootimage_linux.elf.
File conversion complete!
Number of Input Files 1

-rw-rw-r-- 1 gunter gunter 1395240 Oct 31 16:29 tiubootimage_linux.appimage
-rwxrwxr-x 1 gunter gunter 1461296 Oct 31 16:29 tiubootimage_linux.elf*
-rw-rw-r-- 1 gunter gunter 1395208 Oct 31 16:29 tiubootimage_linux.rprc

Writing this appimage into OSPI at 0x7C0000, it also does not print out any u-boot banner after the ATF/OPTEE prints.

How should the right u-boot appimage be created?

Thanks!

--Gunter

Gunter,

In the constructappimageshlos.sh script I added the bold line:

# Defines which appimages this script will create
if [ $OS == "linux" ]; then
GenFiles=("atf_optee" \
"tidtb_linux" \
"tiuboot_linux" \
"tikernelimage_linux"
);

And correspondingly I created a file: mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/linux/tiuboot_linux.lds

Contents:

/*
 * tikernelimage_linux.lds - simple linker file for stand-alone Linux kernel booting
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE.txt file.
 */
OUTPUT_FORMAT("elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
TARGET(binary)
INPUT(u-boot.img)
SECTIONS
{
 . = 0x0000000080080000;
 ubootimage = .;
 .ubootimage : { u-boot.img }
}

Then i ran: ./constructappimageshlos.sh 

Generating atf_optee image
WARNING: The runtime version supported by this application is unavailable.
Using default runtime: v4.0.30319
Parsing the input object file, /home/keerthy/work/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/../../binary/bin/j721e_evm/atf_optee.elf.
File conversion complete!
Number of Input Files 1

Generating tidtb_linux image
WARNING: The runtime version supported by this application is unavailable.
Using default runtime: v4.0.30319
Parsing the input object file, /home/keerthy/work/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/../../binary/bin/j721e_evm/tidtb_linux.elf.
File conversion complete!
Number of Input Files 1

Generating tiuboot_linux image
WARNING: The runtime version supported by this application is unavailable.
Using default runtime: v4.0.30319
Parsing the input object file, /home/keerthy/work/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/../../binary/bin/j721e_evm/tiuboot_linux.elf.
File conversion complete!
Number of Input Files 1

Generating tikernelimage_linux image
WARNING: The runtime version supported by this application is unavailable.
Using default runtime: v4.0.30319
Parsing the input object file, /home/keerthy/work/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/mcusw/mcuss_demos/boot_app_mcu_rtos/main_domain_apps/scripts/hlos/../../binary/bin/j721e_evm/tikernelimage_linux.elf.
File conversion complete!
Number of Input Files 1

ls -l ../../binary/bin/j721e_evm/tiuboot_linux.appimage
-rw-rw-r-- 1 keerthy keerthy 1276548 Nov 5 00:25 ../../binary/bin/j721e_evm/tiuboot_linux.appimage

Can you try generating like above and flash it 0x7C0000 instead of Linux Image?

Note: I have not boot tested. Just compiled it.

Best Regards,
Keerthy

Hi Keerthy,

yes, we can try this, to generate the appimage directly from u-boot.img and flash it. Will get back shortly.

Regards,

--Gunter

Hi Keerthy,

I have tested with u-boot.img and lds file set to entry point 0x80080000, which was what was used in the kernel lds file. However unfortunately there is no printout after ATF/OPTEE.

When the ATF/OPTEE prints complete, using CCS to intercept the A72 core to check where it is, the result was PC = 0x200, where there is no code.

Also I have used u-boot.bin to generate the appimage from, again for 0x80080000, but the symptom is the same, there is no printout.

Here when intercepting, the PC was in a range of DDR at around 0x8011xxxx, with code.

Then finally in that state I loaded the true ELF binary of u-boot (u-boot without extension). This then placed the PC at the true entry point, with is at symbol _start at 0x80800000.

Somehow I feel we are not starting u-boot in the right place. Possible ATF/OPTEE are not branching to a location where u-boot would actually start.

Regards,

--Gunter

Hi Keerthy,

I ran a test with the u-boot-spl instead, as the u-boot-spl has the same entry point as the kernel, that is 0x80080000.

Here is the lds file

/*
 * tiubootspl_linux.lds - simple linker file for stand-alone Linux kernel booting
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE.txt file.
 */
OUTPUT_FORMAT("elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
TARGET(binary)
INPUT(u-boot-spl.bin)
SECTIONS
{
 . = 0x0000000080080000;
 ubootimage = .;
 .ubootimage : { u-boot-spl.bin }
}

Then I added the tiubootspl_linux to the construct script

# Defines which appimages this script will create
if [ $OS == "linux" ]; then
    GenFiles=("atf_optee" \
              "tidtb_linux" \
              "tiubootspl_linux" \
              "tiuboot_linux" \
              "tikernelimage_linux"
             );

With this the u-boot-spl actually prints out after the ATF/OPTEE is finished.

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC: 
I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-dirty (Oct 25 2024 - 11:55:47 -0700)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
Detected: J7X-BASE-CPB rev E3
Detected: J7X-VSC8514-ETH rev E2
error getting GPIO lookup name: -22
Trying to boot from SPI
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled

So this proves that the ATF/OPTEE is in fact branching to 0x80080000, and the u-boot-spl has that as the default entry point.

Now the question is how a combined appimage can be made with u-boot-spl and its dtb file, so that it can run properly, and then pull u-boot from the sdcard e.g.

Regards,

--Gunter

Gunter,

Then can load U-Boot to the place where A72 SPL looks for it in OSPI?

fatload mmc 1 ${loadaddr} u-boot.img

sf update $loadaddr 0x280000 $filesize

Best Regards,
Keerthy

Hi Keerthy,

we confirmed that the u-boot comes up, even without making changes to bypass optee. We left the atf/optee binary as is, and just replace the tiuboot_linux.appimage

But we are running into a problem, that is, the ethernet is not coming up, as you can see from your u-boot log above already.

cdns,sierra serdes@5000000: sierra probed
sierra_phy_link link: Timeout waiting for PHY status ready
sierra_phy_link link: PHY: Failed to power on link: -110.
phy_power_on failed!!: -110
Net: am65_cpsw_nuss_port ethernet@46000000port@1: gmii_sel PHY mode NOT SET!: requested: 00000002, gmii_sel: 00000001

U-Boot 2024.04-00001-g0e054b7c-dirty (Nov 05 2024 - 14:22:20 -0800)

SoC:   J721E SR1.1 GP
Model: Texas Instruments J721E SK
ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
Board: J721EX-PM2-SOM rev E8
DRAM:  2 GiB (effective 4 GiB)
Core:  125 devices, 33 uclasses, devicetree: fit
Flash: 0 Bytes
MMC:   mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1
Detected: J7X-BASE-CPB rev E3
Detected: J7X-VSC8514-ETH rev E2
cdns,sierra serdes@5000000: sierra probed
sierra_phy_link link: Timeout waiting for PHY status ready
sierra_phy_link link: PHY: Failed to power on link: -110.
phy_power_on failed!!: -110
Net:   am65_cpsw_nuss_port ethernet@46000000port@1: gmii_sel PHY mode NOT SET!: requested: 00000002, gmii_sel: 00000001
eth0: ethernet@46000000port@1
Hit any key to stop autoboot:  0 
=>

It looks like the SGMII PHY is not initialized correctly.

A normal u-boot from sdcard e.g shows the proper ethernet come up

am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1

U-Boot 2024.04-ti-g818c76aed67f (Aug 01 2024 - 19:19:47 +0000)

SoC:   J721E SR1.1 GP
Model: Texas Instruments J721E SK
Board: J721EX-PM2-SOM rev E8
DRAM:  2 GiB (effective 4 GiB)
Core:  125 devices, 33 uclasses, devicetree: separate
Flash: 0 Bytes
MMC:   mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1
Detected: J7X-BASE-CPB rev E3
Detected: J7X-VSC8514-ETH rev E2
cdns,sierra serdes@5000000: sierra probed
Net:   eth0: ethernet@46000000port@1
Hit any key to stop autoboot:  0 
=>

Regards,

--Gunter

Hi Keerthy,

I am not sure where exactly this serdes phy is being initialized, e.g. on a working regular sdcard u-boot bootup. (maybe in the SPL?)

Also, I am reminded of the fact that we only use u-boot.bin to make the appimage from.

As you know, typically there is u-boot.img, which is a fit image of u-boot.bin and u-boot dtb. Are we maybe missing something from the u-boot dtb??

Thanks!

--Gunter

Posting Tanmay's response here:

Has we unlocked the ctrl mmr registers in SBL? If not, please follow the following FAQ to unlock the ctrl mmr in SBL

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1278947/faq-tda4vl-how-to-resolve-netdev-watchdog-transmit-queue-timed-out-issue-in-linux-a72-in-case-of-sbl-optimized-boot-flow

 - Tanmay

Hi Tanmay and Keerthy,

I just checked with unlocking the CTRLMMR regs in the sbl_cust_img. The u-boot ethernet works now! We can do now e.g. tftp from u-boot command.

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC: 
I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-ti-g818c76aed67f (Aug 01 2024 - 19:19:47 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
Detected: J7X-BASE-CPB rev E3
Detected: J7X-VSC8514-ETH rev E2
error getting GPIO lookup name: -22
Trying to boot from MMC2
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the ima
ge was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the ima
ge was also encrypted


U-Boot 2024.04-ti-g818c76aed67f (Aug 01 2024 - 19:19:47 +0000)

SoC:   J721E SR1.1 GP
Model: Texas Instruments J721E SK
NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024
I/TC: 
I/TC: OP-TEE version: 4.2.0-dev (gcc version 13.3.0 (GCC)) #1 Fri Apr 12 09:51:21 UTC 2024 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot


U-Boot 2024.04-00001-g0e054b7c-dirty (Nov 05 2024 - 14:22:20 -0800)

SoC:   J721E SR1.1 GP
Model: Texas Instruments J721E SK
ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
Board: J721EX-PM2-SOM rev E8
DRAM:  2 GiB (effective 4 GiB)
Core:  125 devices, 33 uclasses, devicetree: fit
Flash: 0 Bytes
MMC:   mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1
Detected: J7X-BASE-CPB rev E3
Detected: J7X-VSC8514-ETH rev E2
cdns,sierra serdes@5000000: sierra probed
Net:   eth0: ethernet@46000000port@1
Hit any key to stop autoboot:  0 
=> setenv serverip 192.168.1.32
=> setenv ipaddr 192.168.1.34
=> tftp $loadaddr sbl_cust_img_mcu1_0_release.tiimage
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@46000000port@1: K3 CPSW: rflow_id_base: 2
link up on port 1, speed 1000, full duplex
Using ethernet@46000000port@1 device
TFTP from server 192.168.1.32; our IP address is 192.168.1.34
Filename 'sbl_cust_img_mcu1_0_release.tiimage'.
Load address: 0x82000000
Loading: #################################################################
         ##  0 Bytes
         242.2 KiB/s
done
Bytes transferred = 340078 (5306e hex)
=>

The patch applied to sbl_main

gunter@Linux-005:~/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/board/k3$ diff -Nurp sbl_main.c.orig sbl_main.c
--- sbl_main.c.orig	2024-11-06 15:03:28.827359640 -0800
+++ sbl_main.c	2024-11-06 15:16:30.000139733 -0800
@@ -245,6 +245,70 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg
 
 };
 
+//GHS--- added to unlock CTRLMMR registers
+#define WKUP_CTRL_MMR0_BASE             0x43000000
+#define MCU_CTRL_MMR0_BASE              0x40f00000
+#define CTRL_MMR0_BASE                  0x00100000
+
+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+*/
+#define CTRL_MMR0_PARTITION_SIZE       0x4000
+
+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
+ * shared register definitions. The same registers are also used for
+ * PADCFG_MMR lock/kick-mechanism.
+*/
+#define CTRLMMR_LOCK_KICK0         0x1008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL      0x68ef3490
+#define CTRLMMR_LOCK_KICK1         0x100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL      0xd172bc5a
+
+
+void CTRL_MMR_unlock(volatile uint32_t baseAddr, uint32_t partition)
+{
+   /* Get the part base address */
+   uint32_t partBaseAddr = baseAddr + (partition * CTRL_MMR0_PARTITION_SIZE);
+
+   /* Unlock the requested partition if locked using two-step sequence */
+   *(volatile uint32_t *)(partBaseAddr + CTRLMMR_LOCK_KICK0) = CTRLMMR_LOCK_KICK0_UNLOCK_VAL;
+   *(volatile uint32_t *)(partBaseAddr + CTRLMMR_LOCK_KICK1) = CTRLMMR_LOCK_KICK1_UNLOCK_VAL;
+}
+
+static void SBL_CTRL_MMR_unlock_all(void)
+{
+   /* Unlock all WKUP_CTRL_MMR0 module registers */
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 0);
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 1);
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 2);
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 3);
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 4);
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 6);
+   CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+   /* Unlock all MCU_CTRL_MMR0 module registers */
+   CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 0);
+   CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 1);
+   CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 2);
+   CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 3);
+   CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 4);
+
+   /* Unlock all CTRL_MMR0 module registers */
+   CTRL_MMR_unlock(CTRL_MMR0_BASE, 0);
+   CTRL_MMR_unlock(CTRL_MMR0_BASE, 1);
+   CTRL_MMR_unlock(CTRL_MMR0_BASE, 2);
+   CTRL_MMR_unlock(CTRL_MMR0_BASE, 3);
+   CTRL_MMR_unlock(CTRL_MMR0_BASE, 5);
+    #if defined(SOC_J721E)
+       CTRL_MMR_unlock(CTRL_MMR0_BASE, 6);
+   #endif
+   CTRL_MMR_unlock(CTRL_MMR0_BASE, 7);
+}
+//GHS--- 
+
 int main()
 {
     int32_t retVal = CSL_PASS;
@@ -275,6 +339,10 @@ int main()
     /* Any SoC specific Init. */
     SBL_SocEarlyInit();
 
+    //GHS--- Added to unlock CTRLMMR registers
+    /* Unlock control MMR registers */
+    SBL_CTRL_MMR_unlock_all();
+
     if (SBL_LOG_LEVEL > SBL_LOG_ERR)
     {
         /* Configure UART Tx pinmux. */
         

Making the sbl_cust_img

gunter@Linux-005:~/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/build$ make -s sbl_cust_img BOARD=j721e_evm
# Compiling j721e_evm:j721e:mcu1_0:release:sbl_cust_img:sbl_main.c
# Linking into /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release.xer5f...
#
#
# /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release.xer5f created.
#
# Generating stripped image into /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release_strip.xer5f...
#
~/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/board/k3 ~/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/board/k3

Debug Extension is Enabled :
SoC UID not specified for Debug Extension. Using UID 0
	UID = 0000000000000000000000000000000000000000000000000000000000000000
	DBG_TYPE = 4
R5 Certificate being generated :
	X509_CFG = ./x509-temp.cfg
	KEY = /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/build/makerules/rom_degenerateKey.pem
	BIN = /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release.bin
	CERT TYPE = R5, 1
	CORE ID = 16
	LOADADDR = 0x41c00100
	IMAGE_SIZE = 339016
	BOOT_OPTIONS = 2
Certificate being generated :
SUCCESS: Image /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release.tiimage generated. Good to boot
# SBL image /home/gunter/ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/boot/sbl/binary/j721e_evm/cust/bin/sbl_cust_img_mcu1_0_release.bin created.
#

Then the sbl_cust_img_mcu1_0_release.tiimage was flashed into the OSPI.

Regards,

--Gunter