TDA4VEN-Q1: How to use the C7x's DMA in Entry sdk 10.0，update a patch in sdk 10.0

xie jc

Part Number: TDA4VEN-Q1
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi TI experts,

We are currently evaluating C7X core on TDA4VEN chip based on this SDK version.
It is planned to port the functionality of the UDMA of the TDA4's C6X core to ENTRY's C7X core. The UDMA function is used to copy image, which is in order to save C7 CPU resource.

But at present debugging down, from the SDK c7x demo code found that SOC_J722S chip C7X does not seem to support DMA.

Source location: vision_apps\apps\basic_demos\app_c7x_kernel\c7x\app_c7x_target_kernel_img_add.cpp
The source code is shown in the following figure:

#if defined(x86_64) || defined(SOC_AM62A) || defined(SOC_J722S)
#undef USE_HW_DMA
#else
#define USE_HW_DMA
#endif

1. And then，Joe give a new dma demo and patch in entry SDK9.2 ，such as：

dma_demo.rar

2. But now, I can't use this patch in sdk 10.0. Could you update a new dma demo and patch in SDK 10.0？

Thanks.

10 months ago

0 Asha Bhandarkar 10 months ago

TI__Genius 10170 points

Hi,

Thank you for posting your question. Your question has been assigned to the appropriate engineer, however please expect a response next week due to TI holidays this week.

Best,

Asha

0 Brijesh Jadav 10 months ago in reply to Asha Bhandarkar

TI__Guru**** 476725 points

Hi,

There isn't UDMA available on the TDA4AEN device. There is a BCDMA, but it isn't still available in the SDK level, so we can't enable this macro to support DMA on C7x.

Regards,

Brijesh

0 xie jc 10 months ago

Expert 2180 points

Hi，

So there is a demo in the SDK 9.2 to use dru. Could you give a new demo to use dru in the sdk 10.0?

The SDK9,2 demo has posted here，liked the dma_demo.rar in this issue.

Thanks

0 Brijesh Jadav 10 months ago in reply to xie jc

TI__Guru**** 476725 points

Hi JC,

No, there isn't demo available to use DRU on in the SDK yet.

Regards,

Brijesh

0 xie jc 10 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi,

I have 2 questions about the DRU and DMA.

1. How many free DRU channels are available, which can be used for us.

2. In the SDK10.0, there is no demo for the dma in the C7x. In the future, which SDK can support the demo of DMA in the C7x？

Thanks

0 Brijesh Jadav 8 months ago in reply to xie jc

TI__Guru**** 476725 points

Hi jc,

For the number of Free DRU channels, i would request you to refer to sysconfig tool. This will tell us resources allocated to each core.

We are still working on enabling this feature in the SDK.

Regards,

Brijesh

0 Rahul Ravikumar 6 months ago in reply to Brijesh Jadav

TI__Expert 4158 points

Hi Jc,

Please find the attached patch on 10.0 SDK to enable UDMA utils for J722S
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_J722S_2D00_C7x_2D00_Enable_2D00_UDMA_2D00_Utils.patch

Note that the test uses BCDMA, DRU example will be enabled in 11.0 SDK release scheduled in May

Regards
Rahul T R

0 Rahul Ravikumar 6 months ago in reply to Rahul Ravikumar

TI__Expert 4158 points

Hi Jc,

Please ignore the patch shared in last reply
Here is the updated patch with DRU support

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/4760.0001_2D00_j722s_2D00_c7x_2D00_Enable_2D00_UDMA_2D00_utils.patch

Please refer to below function

appUdmaTest1DCopy

in file app_utils/utils/udma/src/app_udma_test.c
for reference on how to use udma_utils API to do
ND copy using DRU on C7x

Regards
Rahul T R

0 xie jc 6 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R

The basic version of this patch is different from ours, especially the basic version of dmautils_autoincrement_3d.c is different from ours, there is no #if below

patch:

@@ -158,7 +158,7 @@ static inline uintptr_t DmaUtilsAutoInc3d_getPhysicalAddress(const DmaUtilsAutoI
const uintptr_t virtualAddr,int32_t chNum)
{
uintptr_t phyAddr = virtualAddr;
- #if (defined(SOC_AM62A) || defined(SOC_AM62DX)) && defined (MCU_PLUS_SDK) &&!defined(HOST_EMULATION)
+ #if defined (MCU_PLUS_SDK) &&!defined(HOST_EMULATION)
Udma_DrvHandleInt udmaDrvHandle = (Udma_DrvHandleInt) dmautilsContext -> initParams.udmaDrvHandle;
#else
Udma_DrvHandle udmaDrvHandle = (Udma_DrvHandle) dmautilsContext -> initParams.udmaDrvHandle;

my code:

static inline uintptr_t DmaUtilsAutoInc3d_getPhysicalAddress(const DmaUtilsAutoInc3d_Context * dmautilsContext,
const uintptr_t virtualAddr,int32_t chNum)
{
uintptr_t phyAddr = virtualAddr;

Udma_DrvHandle udmaDrvHandle = (Udma_DrvHandle) dmautilsContext -> initParams.udmaDrvHandle;
/* If virtual to physical address conversion function is available then use it for
conversion else directly program the address as it is */
if (udmaDrvHandle -> initPrms.virtToPhyFxn != NULL)
{
phyAddr = (uintptr_t) udmaDrvHandle -> initPrms.virtToPhyFxn((void * ) virtualAddr,(uint32_t) chNum,NULL);
}
return phyAddr;
}

From the directory name that you used mcu_plus_sdk_j722s_10_01_00_22 and we are still mcu_plus_sdk_j722s_10_00_00_25.
What about this? dmautils_autoincrement_3d_priv.h, dmautils_autoincrement_3d.c, have similar problems.
Thanks!

0 Rahul Ravikumar 6 months ago in reply to xie jc

TI__Expert 4158 points

Hi Jc,

Sorry about the confusion, I generated the patch on 10.1 SDK
Can you please migrate to 10.1 SDK

PROCESSOR-SDK-RTOS-J722S Software development kit (SDK) | TI.com

Regards
Rahul T R

0 xie jc 6 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R，

Could you provide a patch based on 10.0? Because we are using the 10.0 SDK and have no plan to upgrade.

Thanks!

0 Rahul Ravikumar 5 months ago in reply to xie jc

TI__Expert 4158 points

Hi Jc,

Please find the patch for 10.0
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/6558.0001_2D00_j722s_2D00_c7x_2D00_Enable_2D00_UDMA_2D00_utils.patch

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R,

Please provide a demo to verify this pacth.

See a similar demo in "dma_demo.rar" provided by Joe above.

Thanks!

0 Rahul Ravikumar 5 months ago in reply to xie jc

TI__Expert 4158 points

Hi Jc,

I have already added the function call in c7x main in the patch

+ #ifdef CPU_c7x_1
+ appLogPrintf("APP: UDMA Test !!!\n");
+ appUdmaTest();
+ appLogPrintf("APP: UDMA Test Done !!!\n");
+ #endif
+

This will verify the functionality
you can check the remote core logs using below command

cd /opt/vision_apps
source ./vision_apps_init.sh

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R,

Thank you very much for your support. At present, the result of running your test case is passing.

Thanks!

0 Rahul Ravikumar 5 months ago in reply to xie jc

TI__Expert 4158 points

Hi JC,

Can you please mark the solution as verified
So that I can close the thread

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R,

The patch has been applied and the provided test cases can be run successfully.

However, when running our software, there was a model named tivxAlgiVisionProcess() function that caused the entire C7 core to crash. Of course, this issue does not occur when running another model. Is there any idea or suspicion about this?

We haven't made any modification to our software.

Thanks!

0 Rahul Ravikumar 5 months ago in reply to xie jc

TI__Expert 4158 points

Hi Jc,

This might not be related to this patch,
Can you please revert the patch and try the same model

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R，

Yes, my model worked fine before I patched it.
Or, we don't know if there will be any changes on the model side with this patch? I heard that the model itself is useful for DRU.

Thanks!

0 Rahul Ravikumar 5 months ago in reply to xie jc

TI__Expert 4158 points

Hi Jc,

I did test TIDL with this patch,
Are you using DRU only for TIDL?
or you are using DRU for some other
purpose as well?

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul T R,

We plan to use DRU in other nodes of the graph.
However, we have made a patch now, but our software has not been changed in order to test whether this patch has any influence on us. Therefore, it has been tested that the tidl node of this model will make the C7 core not work after using this patch.

Thanks!

0 TommySong 5 months ago in reply to xie jc

TI__Genius 9520 points

Summary in today's call:

- Applied the patch 6558.0001-j722s-c7x-Enable-UDMA-utils.patch and didn't change any other code

- Then, run the previously workable case will cause C7x core crash.

- One model can work and there is another model will failed at call tivxAlgiVisionProcess()

Need to further check whether any other changes in model or application side after applying the patches.

0 Rahul Ravikumar 5 months ago in reply to TommySong

TI__Expert 4158 points

Hi TommySong,

Can you please confirm, you have scrubbed the SDK and built after applying the patch

make sdk_scrub
make sdk -j16

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul,

The board has been brushed with the patched compilation. But the result is the same.

0 Rahul Ravikumar 5 months ago in reply to xie jc

TI__Expert 4158 points

Hi xie jc,

We don't release some of the TIDL source code, instead we release it as library
And this library depends on dma utils
I guess this library needs rebuild

This feature is part of our 11.0 release which will happen in May mid, I would suggest migration to 11.00 for using this feature

Regards
Rahul T R

0 Rahul Ravikumar 5 months ago in reply to Rahul Ravikumar

TI__Expert 4158 points

Hi xie jc,

Is it possible to share the model artifacts (network and io bins) for failing model
So that I can reproduce the issue at my end?

Regards
Rahul T R

0 xie jc 5 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul,

At present, our model is going through the outbound process.
Synchronizing a message, I also found C7X stuck while verifying the copy of the 3D (WHC) data. And the source data will be tampered with.
Attached are log and testCase, when C=2, the source data of the second channel will be tampered with, and there will be a deadlock in accessing the source data.

Thanks!

Fullscreen 464331.log.txt Download

root@j722s-evm:~# /opt/vx_app_arm_remote_log.out
[MCU2_0]   8371.086022 s: CIO: Init ... Done !!!
[MCU2_0]   8371.086043 s: CPU is running FreeRTOS
[MCU2_0]   8371.086055 s: APP: Init ... !!!
[MCU2_0]   8371.785864 s: SCICLIENT: Init ... !!!
[MCU2_0]   8371.785929 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)]
[MCU2_0]   8371.785945 s: SCICLIENT: DMSC FW revision 0xa
[MCU2_0]   8371.785958 s: SCICLIENT: DMSC FW ABI revision 4.0
[MCU2_0]   8371.785973 s: SCICLIENT: Init ... Done !!!
[MCU2_0]   8371.785985 s: MEM: Init ... !!!
[MCU2_0]   8371.785998 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ b6100000 of size 2097152 bytes !!!
[MCU2_0]   8371.786023 s: MEM: Init ... Done !!!
[MCU2_0]   8371.786035 s: IPC: Init ... !!!
[MCU2_0]   8371.786048 s: IPC: 4 CPUs participating in IPC !!!
[MCU2_0]   8371.786230 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]   8374.096061 s: IPC: HLOS is ready !!!
[MCU2_0]   8374.096097 s: appIpcInit: 1003: IPC: RPMessage_announce() for rpmsg-proto success
[MCU2_0]   8374.096143 s: IPC: Init ... Done !!!
[MCU2_0]   8374.096160 s: APP: Syncing with 3 CPUs ... !!!
[MCU2_0]   8374.096208 s: ---------- mv_info: appLogCpuSyncInit:463: master sync with slave: C7X_1 id:3
[MCU2_0]   8374.096254 s: ---------- mv_info: appLogCpuSyncInit:465: master sync with slave: C7X_1 id:3 done
[MCU2_0]   8374.096295 s: ---------- mv_info: appLogCpuSyncInit:463: master sync with slave: C7X_2 id:4
[MCU2_0]   8374.096337 s: ---------- mv_info: appLogCpuSyncInit:465: master sync with slave: C7X_2 id:4 done
[MCU2_0]   8374.096377 s: ---------- mv_info: appLogCpuSyncInit:496: master start slave: C7X_1 id:3
[MCU2_0]   8374.096416 s: ---------- mv_info: appLogCpuSyncInit:498: master start slave: C7X_1 id:3 done
[MCU2_0]   8374.096454 s: ---------- mv_info: appLogCpuSyncInit:496: master start slave: C7X_2 id:4
[MCU2_0]   8374.096496 s: ---------- mv_info: appLogCpuSyncInit:498: master start slave: C7X_2 id:4 done
[MCU2_0]   8374.096513 s: APP: Syncing with 3 CPUs ... Done !!!
[MCU2_0]   8374.096527 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]   8374.097085 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]   8374.097107 s: FVID2: Init ... !!!
[MCU2_0]   8374.097134 s: FVID2: Init ... Done !!!
[MCU2_0]   8374.097146 s: VHWA: VPAC Init ... !!!
[MCU2_0]   8374.097158 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
[MCU2_0]   8374.097230 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.097411 s: VHWA: LDC Init ... !!!
[MCU2_0]   8374.097633 s: VHWA: LDC Init ... Done !!!
[MCU2_0]   8374.097652 s: VHWA: MSC Init ... !!!
[MCU2_0]   8374.098462 s: VHWA: MSC Init ... Done !!!
[MCU2_0]   8374.098480 s: VHWA: VISS Init ... !!!
[MCU2_0]   8374.099389 s: VHWA: VISS Init ... Done !!!
[MCU2_0]   8374.099415 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]   8374.099428 s: VHWA: DMPAC: Init ... !!!
[MCU2_0]   8374.099439 s: SCICLIENT: Sciclient_pmSetModuleState module=277 state=2
[MCU2_0]   8374.099513 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.099526 s: VHWA: DOF Init ... !!!
[MCU2_0]   8374.099619 s: VHWA: DOF Init ... Done !!!
[MCU2_0]   8374.099635 s: VHWA: SDE Init ... !!!
[MCU2_0]   8374.099698 s: VHWA: SDE Init ... Done !!!
[MCU2_0]   8374.099712 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_0]   8374.099735 s:  VX_ZONE_INIT:Enabled
[MCU2_0]   8374.099749 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]   8374.099762 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]   8374.100274 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target MCU2-0
[MCU2_0]   8374.100339 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target VPAC_LDC1
[MCU2_0]   8374.100393 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target VPAC_MSC1
[MCU2_0]   8374.100450 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target VPAC_MSC2
[MCU2_0]   8374.100551 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target VPAC_VISS1
[MCU2_0]   8374.100624 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target CAPTURE1
[MCU2_0]   8374.100695 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target CAPTURE2
[MCU2_0]   8374.100762 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target CAPTURE3
[MCU2_0]   8374.100829 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target CAPTURE4
[MCU2_0]   8374.100896 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DISPLAY1
[MCU2_0]   8374.100963 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DISPLAY2
[MCU2_0]   8374.101026 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target CSITX
[MCU2_0]   8374.101087 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target CSITX2
[MCU2_0]   8374.101149 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DMPAC_SDE
[MCU2_0]   8374.101201 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DMPAC_DOF
[MCU2_0]   8374.101224 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
[MCU2_0]   8374.101238 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]   8374.105933 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]   8374.105956 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0]   8374.106092 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0]   8374.106114 s: CSI2RX: Init ... !!!
[MCU2_0]   8374.106125 s: SCICLIENT: Sciclient_pmSetModuleState module=182 state=2
[MCU2_0]   8374.106161 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.106175 s: SCICLIENT: Sciclient_pmSetModuleState module=247 state=2
[MCU2_0]   8374.106224 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.106237 s: SCICLIENT: Sciclient_pmSetModuleState module=185 state=2
[MCU2_0]   8374.106273 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.106286 s: SCICLIENT: Sciclient_pmSetModuleState module=251 state=2
[MCU2_0]   8374.106321 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.106468 s: CSI2RX: Init ... Done !!!
[MCU2_0]   8374.106485 s: CSI2TX: Init ... !!!
[MCU2_0]   8374.106496 s: SCICLIENT: Sciclient_pmSetModuleState module=250 state=2
[MCU2_0]   8374.106546 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.106559 s: SCICLIENT: Sciclient_pmSetModuleState module=238 state=2
[MCU2_0]   8374.106598 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   8374.106611 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=250 clk=3 freq=16000000
[MCU2_0]   8374.106660 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]   8374.106676 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=250 clk=4 freq=500000000
[MCU2_0]   8374.106720 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]   8374.106749 s: CSI2TX: Init ... Done !!!
[MCU2_0]   8374.106763 s: ISS: Init ... !!!
[MCU2_0]   8374.106784 s: IssSensor_Init ... Done !!!
[MCU2_0]   8374.106829 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]   8374.106842 s: ISS: Init ... Done !!!
[MCU2_0]   8374.106856 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]   8374.106894 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]   8374.106913 s: APP: Init ... Done !!!
[MCU2_0]   8374.106926 s: APP: Run ... !!!
[MCU2_0]   8374.106937 s: IPC: Starting echo test ...
[MCU2_0]   8374.106994 s: APP: Run ... Done !!!
[MCU2_0]   8374.107020 s: I2C Instance = 0
[MCU2_0]   8374.107037 s: write i=0
[MCU2_0]   8374.112049 s: write i=1
[MCU2_0]   8374.117048 s: write i=2
[MCU2_0]   8374.122093 s: @0x42 write 0x0001 for value 0x14, readback: 0xFF, status = -1
[MCU2_0]   8374.122118 s: write i=0
[MCU2_0]   8374.127049 s: write i=1
[MCU2_0]   8374.132049 s: write i=2
[MCU2_0]   8374.137094 s: @0x42 write 0x0331 for value 0x33, readback: 0xFF, status = -1
[MCU2_0]   8374.137117 s: write i=0
[MCU2_0]   8374.153051 s: write i=1
[MCU2_0]   8374.169052 s: write i=2
[MCU2_0]   8374.185096 s: @0x42 write 0x0318 for value 0x64, readback: 0xFF, status = -1
[MCU2_0]   8374.185120 s: MAX9295 init status 0
[MCU2_0]   8399.087047 s: ---------- mv_info: appMain:140: MCU2_0 is running
[MCU2_0]   8426.089206 s: ---------- mv_info: appMain:140: MCU2_0 is running
[C7x_1 ]   8371.223735 s: CIO: Init ... Done !!!
[C7x_1 ]   8371.223753 s: CPU is running FreeRTOS
[C7x_1 ]   8371.223765 s: APP: Init ... !!!
[C7x_1 ]   8371.923308 s: SCICLIENT: Init ... !!!
[C7x_1 ]   8371.923372 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)]
[C7x_1 ]   8371.923390 s: SCICLIENT: DMSC FW revision 0xa
[C7x_1 ]   8371.923403 s: SCICLIENT: DMSC FW ABI revision 4.0
[C7x_1 ]   8371.923416 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]   8371.923427 s: UDMA: Init ... !!!
[C7x_1 ]   8371.923452 s: UDMA: Init ... Done !!!
[C7x_1 ]   8371.923465 s: MEM: Init ... !!!
[C7x_1 ]   8371.923477 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102e00000 of size 67108864 bytes !!!
[C7x_1 ]   8371.923503 s: MEM: Init ... Done !!!
[C7x_1 ]   8371.923514 s: IPC: Init ... !!!
[C7x_1 ]   8371.923524 s: IPC: 4 CPUs participating in IPC !!!
[C7x_1 ]   8371.923791 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]   8374.046569 s: IPC: HLOS is ready !!!
[C7x_1 ]   8374.046599 s: appIpcInit: 1003: IPC: RPMessage_announce() for rpmsg-proto success
[C7x_1 ]   8374.046660 s: IPC: Init ... Done !!!
[C7x_1 ]   8374.046675 s: APP: Syncing with 3 CPUs ... !!!
[C7x_1 ]   8374.046711 s: ---------- mv_info: appLogCpuSyncInit:525: slave: C7X_1 id:3 sync with master
[C7x_1 ]   8374.096416 s: ---------- mv_info: appLogCpuSyncInit:527: slave: C7X_1 id:3 sync with master done
[C7x_1 ]   8374.096436 s: APP: Syncing with 3 CPUs ... Done !!!
[C7x_1 ]   8374.096450 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]   8374.097568 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]   8374.097629 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]   8374.097645 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]   8374.097659 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]   8374.098455 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1
[C7x_1 ]   8374.098556 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_2
[C7x_1 ]   8374.098656 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_3
[C7x_1 ]   8374.098760 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_4
[C7x_1 ]   8374.098862 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_5
[C7x_1 ]   8374.098954 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_6
[C7x_1 ]   8374.099043 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_7
[C7x_1 ]   8374.099134 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-1_PRI_8
[C7x_1 ]   8374.099161 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
[C7x_1 ]   8374.099177 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]   8374.099760 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]   8374.099777 s: APP: Init ... Done !!!
[C7x_1 ]   8374.099787 s: APP: UDMA Test !!!
[C7x_1 ]   8374.099797 s: UDMA: Test ... !!!
[C7x_1 ]   8374.099818 s: [2,5,1] 464: 129
[C7x_1 ]   8374.099833 s: [3,5,1] 465: 130
[C7x_1 ]   8374.099849 s: [4,5,1] 466: 131
[C7x_1 ]   8374.099861 s: [5,5,1] 467: 132
[C7x_1 ]   8374.099873 s: [6,5,1] 468: 133
[C7x_1 ]   8374.099885 s: [7,5,1] 469: 134
[C7x_1 ]   8374.099896 s: [8,5,1] 470: 135
[C7x_1 ]   8374.099909 s: [9,5,1] 471: 136
[C7x_1 ]   8374.099921 s: [10,5,1] 472: 137
[C7x_1 ]   8374.099933 s: [11,5,1] 473: 138
[C7x_1 ]   8374.099945 s: [12,5,1] 474: 139
[C7x_1 ]   8374.099956 s: [13,5,1] 475: 140
[C7x_1 ]   8374.099968 s: [14,5,1] 476: 141
[C7x_1 ]   8374.099979 s: [15,5,1] 477: 142
[C7x_1 ]   8374.099991 s: [16,5,1] 478: 143
[C7x_1 ]   8374.100003 s: [17,5,1] 479: 144
[C7x_1 ]   8374.100016 s: [2,6,1] 486: 145
[C7x_1 ]   8374.100028 s: [3,6,1] 487: 146
[C7x_1 ]   8374.100039 s: [4,6,1] 488: 147
[C7x_1 ]   8374.100051 s: [5,6,1] 489: 148
[C7x_1 ]   8374.100063 s: [6,6,1] 490: 149
[C7x_1 ]   8374.100074 s: [7,6,1] 491: 150
[C7x_1 ]   8374.100086 s: [8,6,1] 492: 151
[C7x_1 ]   8374.100098 s: [9,6,1] 493: 152
[C7x_1 ]   8374.100109 s: [10,6,1] 494: 153
[C7x_1 ]   8374.100121 s: [11,6,1] 495: 154
[C7x_1 ]   8374.100133 s: [12,6,1] 496: 155
[C7x_1 ]   8374.100145 s: [13,6,1] 497: 156
[C7x_1 ]   8374.100156 s: [14,6,1] 498: 157
[C7x_1 ]   8374.100168 s: [15,6,1] 499: 158
[C7x_1 ]   8374.100180 s: [16,6,1] 500: 159
[C7x_1 ]   8374.100192 s: [17,6,1] 501: 160
[C7x_1 ]   8374.100203 s: [2,7,1] 508: 161
[C7x_1 ]   8374.100215 s: [3,7,1] 509: 162
[C7x_1 ]   8374.100226 s: [4,7,1] 510: 163
[C7x_1 ]   8374.100238 s: [5,7,1] 511: 164
[C7x_1 ]   8374.100250 s: [6,7,1] 512: 165
[C7x_1 ]   8374.100262 s: [7,7,1] 513: 166
[C7x_1 ]   8374.100273 s: [8,7,1] 514: 167
[C7x_1 ]   8374.100285 s: [9,7,1] 515: 168
[C7x_1 ]   8374.100297 s: [10,7,1] 516: 169
[C7x_1 ]   8374.100308 s: [11,7,1] 517: 170
[C7x_1 ]   8374.100320 s: [12,7,1] 518: 171
[C7x_1 ]   8374.100332 s: [13,7,1] 519: 172
[C7x_1 ]   8374.100344 s: [14,7,1] 520: 173
[C7x_1 ]   8374.100356 s: [15,7,1] 521: 174
[C7x_1 ]   8374.100367 s: [16,7,1] 522: 175
[C7x_1 ]   8374.100379 s: [17,7,1] 523: 176
[C7x_1 ]   8374.100391 s: [2,8,1] 530: 177
[C7x_1 ]   8374.100403 s: [3,8,1] 531: 178
[C7x_1 ]   8374.100414 s: [4,8,1] 532: 179
[C7x_1 ]   8374.100426 s: [5,8,1] 533: 180
[C7x_1 ]   8374.100437 s: [6,8,1] 534: 181
[C7x_1 ]   8374.100449 s: [7,8,1] 535: 182
[C7x_1 ]   8374.100461 s: [8,8,1] 536: 183
[C7x_1 ]   8374.100473 s: [9,8,1] 537: 184
[C7x_1 ]   8374.100493 s: [10,8,1] 538: 185
[C7x_1 ]   8374.100506 s: [11,8,1] 539: 186
[C7x_1 ]   8374.100518 s: [12,8,1] 540: 187
[C7x_1 ]   8374.100530 s: [13,8,1] 541: 188
[C7x_1 ]   8374.100541 s: [14,8,1] 542: 189
[C7x_1 ]   8374.100553 s: [15,8,1] 543: 190
[C7x_1 ]   8374.100565 s: [16,8,1] 544: 191
[C7x_1 ]   8374.100577 s: [17,8,1] 545: 192
[C7x_1 ]   8374.100589 s: [2,9,1] 552: 193
[C7x_1 ]   8374.100600 s: [3,9,1] 553: 194
[C7x_1 ]   8374.100612 s: [4,9,1] 554: 195
[C7x_1 ]   8374.100624 s: [5,9,1] 555: 196
[C7x_1 ]   8374.100636 s: [6,9,1] 556: 197
[C7x_1 ]   8374.100647 s: [7,9,1] 557: 198
[C7x_1 ]   8374.100659 s: [8,9,1] 558: 199
[C7x_1 ]   8374.100670 s: [9,9,1] 559: 200
[C7x_1 ]   8374.100682 s: [10,9,1] 560: 201
[C7x_1 ]   8374.100694 s: [11,9,1] 561: 202
[C7x_1 ]   8374.100706 s: [12,9,1] 562: 203
[C7x_1 ]   8374.100718 s: [13,9,1] 563: 204
[C7x_1 ]   8374.100730 s: [14,9,1] 564: 205
[C7x_1 ]   8374.100741 s: [15,9,1] 565: 206
[C7x_1 ]   8374.100753 s: [16,9,1] 566: 207
[C7x_1 ]   8374.100765 s: [17,9,1] 567: 208
[C7x_1 ]   8374.100777 s: [2,10,1] 574: 209
[C7x_1 ]   8374.100788 s: [3,10,1] 575: 210
[C7x_1 ]   8374.100800 s: [4,10,1] 576: 211
[C7x_1 ]   8374.100813 s: [5,10,1] 577: 212
[C7x_1 ]   8374.100825 s: [6,10,1] 578: 213
[C7x_1 ]   8374.100836 s: [7,10,1] 579: 214
[C7x_1 ]   8374.100848 s: [8,10,1] 580: 215
[C7x_1 ]   8374.100860 s: [9,10,1] 581: 216
[C7x_1 ]   8374.100872 s: [10,10,1] 582: 217
[C7x_1 ]   8374.100884 s: [11,10,1] 583: 218
[C7x_1 ]   8374.100896 s: [12,10,1] 584: 219
[C7x_1 ]   8374.100908 s: [13,10,1] 585: 220
[C7x_1 ]   8374.100920 s: [14,10,1] 586: 221
[C7x_1 ]   8374.100931 s: [15,10,1] 587: 222
[C7x_1 ]   8374.100943 s: [16,10,1] 588: 223
[C7x_1 ]   8374.100955 s: [17,10,1] 589: 224
[C7x_1 ]   8374.100967 s: [2,11,1] 596: 225
[C7x_1 ]   8374.100978 s: [3,11,1] 597: 226
[C7x_1 ]   8374.100990 s: [4,11,1] 598: 227
[C7x_1 ]   8374.101002 s: [5,11,1] 599: 228
[C7x_1 ]   8374.101013 s: [6,11,1] 600: 229
[C7x_1 ]   8374.101025 s: [7,11,1] 601: 230
[C7x_1 ]   8374.101037 s: [8,11,1] 602: 231
[C7x_1 ]   8374.101048 s: [9,11,1] 603: 232
[C7x_1 ]   8374.101060 s: [10,11,1] 604: 233
[C7x_1 ]   8374.101072 s: [11,11,1] 605: 234
[C7x_1 ]   8374.101083 s: [12,11,1] 606: 235
[C7x_1 ]   8374.101095 s: [13,11,1] 607: 236
[C7x_1 ]   8374.101107 s: [14,11,1] 608: 237
[C7x_1 ]   8374.101119 s: [15,11,1] 609: 238
[C7x_1 ]   8374.101131 s: [16,11,1] 610: 239
[C7x_1 ]   8374.101143 s: [17,11,1] 611: 240
[C7x_1 ]   8374.101155 s: [2,12,1] 618: 241
[C7x_1 ]   8374.101167 s: [3,12,1] 619: 242
[C7x_1 ]   8374.101178 s: [4,12,1] 620: 243
[C7x_1 ]   8374.101190 s: [5,12,1] 621: 244
[C7x_1 ]   8374.101202 s: [6,12,1] 622: 245
[C7x_1 ]   8374.101213 s: [7,12,1] 623: 246
[C7x_1 ]   8374.101225 s: [8,12,1] 624: 247
[C7x_1 ]   8374.101236 s: [9,12,1] 625: 248
[C7x_1 ]   8374.101248 s: [10,12,1] 626: 249
[C7x_1 ]   8374.101260 s: [11,12,1] 627: 250
[C7x_1 ]   8374.101272 s: [12,12,1] 628: 251
[C7x_1 ]   8374.101284 s: [13,12,1] 629: 252
[C7x_1 ]   8374.101296 s: [14,12,1] 630: 253
[C7x_1 ]   8374.101308 s: [15,12,1] 631: 254
[C7x_1 ]   8374.101320 s: [16,12,1] 632: 255
[C7x_1 ]   8374.101333 s: [17,12,1] 633: 0
[C7x_1 ]   8374.101350 s: ************************ :262
[C7x_1 ]   8374.101366 s:  # IN ND TR PRMs,
[C7x_1 ]   8374.101376 s:  copy mode = 3
[C7x_1 ]   8374.101387 s:  src       = 882e000b0
[C7x_1 ]   8374.101400 s:  dst       = 882e002c0
[C7x_1 ]   8374.101410 s:  icnt0     = 16
[C7x_1 ]   8374.101419 s:  icnt1     = 8
[C7x_1 ]   8374.101429 s:  icnt2     = 2
[C7x_1 ]   8374.101438 s:  icnt3     = 1
[C7x_1 ]   8374.101446 s:  dicnt0    = 16
[C7x_1 ]   8374.101456 s:  dicnt1    = 8
[C7x_1 ]   8374.101465 s:  dicnt2    = 2
[C7x_1 ]   8374.101481 s:  dicnt3    = 1
[C7x_1 ]   8374.101494 s:  dim1      = 22
[C7x_1 ]   8374.101504 s:  dim2      = 352
[C7x_1 ]   8374.101515 s:  dim3      = 352
[C7x_1 ]   8374.101525 s:  ddim1     = 16
[C7x_1 ]   8374.101536 s:  ddin2     = 128
[C7x_1 ]   8374.101546 s:  ddim3     = 128
[C7x_1 ]   8374.101556 s:
[C7x_1 ]   8374.101564 s:  # OUT ND TR PRMs,
[C7x_1 ]   8374.101575 s:  copy mode = 3
[C7x_1 ]   8374.101586 s:  src       = 882e002c0
[C7x_1 ]   8374.101597 s:  dst       = 882e00200
[C7x_1 ]   8374.101607 s:  icnt0     = 16
[C7x_1 ]   8374.101616 s:  icnt1     = 8
[C7x_1 ]   8374.101625 s:  icnt2     = 2
[C7x_1 ]   8374.101634 s:  icnt3     = 1
[C7x_1 ]   8374.101644 s:  dicnt0    = 16
[C7x_1 ]   8374.101653 s:  dicnt1    = 8
[C7x_1 ]   8374.101663 s:  dicnt2    = 2
[C7x_1 ]   8374.101672 s:  dicnt3    = 1
[C7x_1 ]   8374.101681 s:  dim1      = 16
[C7x_1 ]   8374.101689 s:  dim2      = 128
[C7x_1 ]   8374.101699 s:  dim3      = 128
[C7x_1 ]   8374.101710 s:  ddim1     = 16
[C7x_1 ]   8374.101719 s:  ddin2     = 128
[C7x_1 ]   8374.101728 s:  ddim3     = 128
[C7x_1 ]   8374.101738 s:
[C7x_1 ]   8374.101746 s: ************************ :266
[C7x_1 ]   8374.101790 s: UDMA : LOG: appUdmaGetClecConfigEvent
[C7x_1 ]   8374.101812 s: ************************ :268
[C7x_1 ]   8374.101862 s: UDMA : LOG: appUdmaGetClecConfigEvent
[C7x_1 ]   8374.101881 s: ************************ :271
[C7x_1 ]   8374.101899 s: ************************ n_blk:1
[C7x_1 ]   8374.101916 s: cur n_blk :0
[C7x_1 ]   8374.101933 s: *********************************************************
[C7x_1 ]   8374.101949 s: --------------------------------
[C7x_1 ]   8374.101960 s: 1
[C7x_1 ]   8374.101969 s: 2
[C7x_1 ]   8374.101979 s: 3
[C7x_1 ]   8374.101986 s: 4
[C7x_1 ]   8374.101993 s: 5
[C7x_1 ]   8374.102000 s: 6
[C7x_1 ]   8374.102008 s: 7
[C7x_1 ]   8374.102015 s: 8
[C7x_1 ]   8374.102022 s: 9
[C7x_1 ]   8374.102030 s: 10
[C7x_1 ]   8374.102038 s: 11
[C7x_1 ]   8374.102047 s: 12
[C7x_1 ]   8374.102055 s: 13
[C7x_1 ]   8374.102063 s: 14
[C7x_1 ]   8374.102070 s: 15
[C7x_1 ]   8374.102078 s: 16
[C7x_1 ]   8374.102088 s: --------------------------------
[C7x_1 ]   8374.102100 s: 17
[C7x_1 ]   8374.102108 s: 18
[C7x_1 ]   8374.102116 s: 19
[C7x_1 ]   8374.102124 s: 20
[C7x_1 ]   8374.102131 s: 21
[C7x_1 ]   8374.102139 s: 22
[C7x_1 ]   8374.102146 s: 23
[C7x_1 ]   8374.102153 s: 24
[C7x_1 ]   8374.102160 s: 25
[C7x_1 ]   8374.102168 s: 26
[C7x_1 ]   8374.102175 s: 27
[C7x_1 ]   8374.102185 s: 28
[C7x_1 ]   8374.102193 s: 29
[C7x_1 ]   8374.102201 s: 30
[C7x_1 ]   8374.102208 s: 31
[C7x_1 ]   8374.102216 s: 32
[C7x_1 ]   8374.102224 s: --------------------------------
[C7x_1 ]   8374.102234 s: 33
[C7x_1 ]   8374.102242 s: 34
[C7x_1 ]   8374.102251 s: 35
[C7x_1 ]   8374.102258 s: 36
[C7x_1 ]   8374.102266 s: 37
[C7x_1 ]   8374.102273 s: 38
[C7x_1 ]   8374.102281 s: 39
[C7x_1 ]   8374.102289 s: 40
[C7x_1 ]   8374.102298 s: 41
[C7x_1 ]   8374.102306 s: 42
[C7x_1 ]   8374.102315 s: 43
[C7x_1 ]   8374.102323 s: 44
[C7x_1 ]   8374.102331 s: 45
[C7x_1 ]   8374.102340 s: 46
[C7x_1 ]   8374.102347 s: 47
[C7x_1 ]   8374.102355 s: 48
[C7x_1 ]   8374.102363 s: --------------------------------
[C7x_1 ]   8374.102374 s: 49
[C7x_1 ]   8374.102382 s: 50
[C7x_1 ]   8374.102390 s: 51
[C7x_1 ]   8374.102398 s: 52
[C7x_1 ]   8374.102405 s: 53
[C7x_1 ]   8374.102413 s: 54
[C7x_1 ]   8374.102421 s: 55
[C7x_1 ]   8374.102429 s: 56
[C7x_1 ]   8374.102437 s: 57
[C7x_1 ]   8374.102444 s: 58
[C7x_1 ]   8374.102452 s: 59
[C7x_1 ]   8374.102460 s: 60
[C7x_1 ]   8374.102468 s: 61
[C7x_1 ]   8374.102483 s: 62
[C7x_1 ]   8374.102495 s: 63
[C7x_1 ]   8374.102505 s: 64
[C7x_1 ]   8374.102513 s: --------------------------------
[C7x_1 ]   8374.102523 s: 65
[C7x_1 ]   8374.102530 s: 66
[C7x_1 ]   8374.102538 s: 67
[C7x_1 ]   8374.102546 s: 68
[C7x_1 ]   8374.102554 s: 69
[C7x_1 ]   8374.102562 s: 70
[C7x_1 ]   8374.102569 s: 71
[C7x_1 ]   8374.102577 s: 72
[C7x_1 ]   8374.102584 s: 73
[C7x_1 ]   8374.102592 s: 74
[C7x_1 ]   8374.102600 s: 75
[C7x_1 ]   8374.102608 s: 76
[C7x_1 ]   8374.102618 s: 77
[C7x_1 ]   8374.102625 s: 78
[C7x_1 ]   8374.102633 s: 79
[C7x_1 ]   8374.102641 s: 80
[C7x_1 ]   8374.102649 s: --------------------------------
[C7x_1 ]   8374.102661 s: 81
[C7x_1 ]   8374.102668 s: 82
[C7x_1 ]   8374.102676 s: 83
[C7x_1 ]   8374.102683 s: 84
[C7x_1 ]   8374.102690 s: 85
[C7x_1 ]   8374.102697 s: 86
[C7x_1 ]   8374.102720 s: 87
[C7x_1 ]   8374.102729 s: 88
[C7x_1 ]   8374.102738 s: 89
[C7x_1 ]   8374.102747 s: 90
[C7x_1 ]   8374.102755 s: 91
[C7x_1 ]   8374.102764 s: 92
[C7x_1 ]   8374.102772 s: 93
[C7x_1 ]   8374.102780 s: 94
[C7x_1 ]   8374.102788 s: 95
[C7x_1 ]   8374.102796 s: 96
[C7x_1 ]   8374.102805 s: --------------------------------
[C7x_1 ]   8374.102817 s: 97
[C7x_1 ]   8374.102824 s: 98
[C7x_1 ]   8374.102831 s: 99
[C7x_1 ]   8374.102839 s: 100
[C7x_1 ]   8374.102846 s: 101
[C7x_1 ]   8374.102854 s: 102
[C7x_1 ]   8374.102861 s: 103
[C7x_1 ]   8374.102869 s: 104
[C7x_1 ]   8374.102877 s: 105
[C7x_1 ]   8374.102885 s: 106
[C7x_1 ]   8374.102892 s: 107
[C7x_1 ]   8374.102900 s: 108
[C7x_1 ]   8374.102908 s: 109
[C7x_1 ]   8374.102917 s: 110
[C7x_1 ]   8374.102925 s: 111
[C7x_1 ]   8374.102933 s: 112
[C7x_1 ]   8374.102942 s: --------------------------------
[C7x_1 ]   8374.102953 s: 113
[C7x_1 ]   8374.102961 s: 114
[C7x_1 ]   8374.102969 s: 115
[C7x_1 ]   8374.102977 s: 116
[C7x_1 ]   8374.102986 s: 117
[C7x_1 ]   8374.102994 s: 118
[C7x_1 ]   8374.103001 s: 119
[C7x_1 ]   8374.103009 s: 120
[C7x_1 ]   8374.103018 s: 121
[C7x_1 ]   8374.103026 s: 122
[C7x_1 ]   8374.103036 s: 123
[C7x_1 ]   8374.103044 s: 124
[C7x_1 ]   8374.103052 s: 125
[C7x_1 ]   8374.103060 s: 126
[C7x_1 ]   8374.103068 s: 127
[C7x_1 ]   8374.103075 s: 128
[C7x_1 ]   8374.103086 s: *********************************************************
[C7x_1 ]   8374.103101 s: --------------------------------
[C7x_1 ]   8374.103113 s: 129
[C7x_1 ]   8374.103121 s: [2,5,1] 464: 17
[C7x_1 ]   8374.103136 s: 129
[C7x_1 ]   8374.103148 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103161 s: 130
[C7x_1 ]   8374.103171 s: [3,5,1] 465: 18
[C7x_1 ]   8374.103182 s: 130
[C7x_1 ]   8374.103191 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103202 s: 131
[C7x_1 ]   8374.103210 s: [4,5,1] 466: 19
[C7x_1 ]   8374.103222 s: 131
[C7x_1 ]   8374.103232 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103241 s: 132
[C7x_1 ]   8374.103249 s: [5,5,1] 467: 20
[C7x_1 ]   8374.103262 s: 132
[C7x_1 ]   8374.103271 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103281 s: 133
[C7x_1 ]   8374.103290 s: [6,5,1] 468: 21
[C7x_1 ]   8374.103302 s: 133
[C7x_1 ]   8374.103311 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103320 s: 134
[C7x_1 ]   8374.103328 s: [7,5,1] 469: 22
[C7x_1 ]   8374.103340 s: 134
[C7x_1 ]   8374.103349 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103358 s: 135
[C7x_1 ]   8374.103366 s: [8,5,1] 470: 23
[C7x_1 ]   8374.103378 s: 135
[C7x_1 ]   8374.103388 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103398 s: 136
[C7x_1 ]   8374.103407 s: [9,5,1] 471: 24
[C7x_1 ]   8374.103418 s: 136
[C7x_1 ]   8374.103426 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103436 s: 137
[C7x_1 ]   8374.103444 s: [10,5,1] 472: 25
[C7x_1 ]   8374.103456 s: 137
[C7x_1 ]   8374.103465 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103483 s: 138
[C7x_1 ]   8374.103497 s: [11,5,1] 473: 26
[C7x_1 ]   8374.103511 s: 138
[C7x_1 ]   8374.103521 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103533 s: 139
[C7x_1 ]   8374.103541 s: [12,5,1] 474: 27
[C7x_1 ]   8374.103553 s: 139
[C7x_1 ]   8374.103561 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103573 s: 140
[C7x_1 ]   8374.103582 s: [13,5,1] 475: 28
[C7x_1 ]   8374.103595 s: 140
[C7x_1 ]   8374.103603 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103613 s: 141
[C7x_1 ]   8374.103621 s: [14,5,1] 476: 29
[C7x_1 ]   8374.103635 s: 141
[C7x_1 ]   8374.103643 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103655 s: 142
[C7x_1 ]   8374.103664 s: [15,5,1] 477: 30
[C7x_1 ]   8374.103676 s: 142
[C7x_1 ]   8374.103684 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103694 s: 143
[C7x_1 ]   8374.103703 s: [16,5,1] 478: 31
[C7x_1 ]   8374.103716 s: 143
[C7x_1 ]   8374.103725 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103736 s: 144
[C7x_1 ]   8374.103743 s: [17,5,1] 479: 32
[C7x_1 ]   8374.103755 s: 144
[C7x_1 ]   8374.103763 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103776 s: --------------------------------
[C7x_1 ]   8374.103788 s: 145
[C7x_1 ]   8374.103795 s: [2,6,1] 486: 39
[C7x_1 ]   8374.103807 s: 145
[C7x_1 ]   8374.103816 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103826 s: 146
[C7x_1 ]   8374.103834 s: [3,6,1] 487: 40
[C7x_1 ]   8374.103846 s: 146
[C7x_1 ]   8374.103855 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103865 s: 147
[C7x_1 ]   8374.103874 s: [4,6,1] 488: 41
[C7x_1 ]   8374.103886 s: 147
[C7x_1 ]   8374.103895 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103906 s: 148
[C7x_1 ]   8374.103913 s: [5,6,1] 489: 42
[C7x_1 ]   8374.103925 s: 148
[C7x_1 ]   8374.103934 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103944 s: 149
[C7x_1 ]   8374.103952 s: [6,6,1] 490: 43
[C7x_1 ]   8374.103965 s: 149
[C7x_1 ]   8374.103974 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.103985 s: 150
[C7x_1 ]   8374.103993 s: [7,6,1] 491: 44
[C7x_1 ]   8374.104005 s: 150
[C7x_1 ]   8374.104013 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104025 s: 151
[C7x_1 ]   8374.104033 s: [8,6,1] 492: 45
[C7x_1 ]   8374.104045 s: 151
[C7x_1 ]   8374.104053 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104063 s: 152
[C7x_1 ]   8374.104071 s: [9,6,1] 493: 46
[C7x_1 ]   8374.104083 s: 152
[C7x_1 ]   8374.104091 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104102 s: 153
[C7x_1 ]   8374.104111 s: [10,6,1] 494: 47
[C7x_1 ]   8374.104124 s: 153
[C7x_1 ]   8374.104132 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104142 s: 154
[C7x_1 ]   8374.104151 s: [11,6,1] 495: 48
[C7x_1 ]   8374.104164 s: 154
[C7x_1 ]   8374.104172 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104184 s: 155
[C7x_1 ]   8374.104191 s: [12,6,1] 496: 49
[C7x_1 ]   8374.104204 s: 155
[C7x_1 ]   8374.104213 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104223 s: 156
[C7x_1 ]   8374.104231 s: [13,6,1] 497: 50
[C7x_1 ]   8374.104242 s: 156
[C7x_1 ]   8374.104250 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104262 s: 157
[C7x_1 ]   8374.104270 s: [14,6,1] 498: 51
[C7x_1 ]   8374.104282 s: 157
[C7x_1 ]   8374.104291 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104301 s: 158
[C7x_1 ]   8374.104309 s: [15,6,1] 499: 52
[C7x_1 ]   8374.104321 s: 158
[C7x_1 ]   8374.104332 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104343 s: 159
[C7x_1 ]   8374.104351 s: [16,6,1] 500: 53
[C7x_1 ]   8374.104363 s: 159
[C7x_1 ]   8374.104371 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104382 s: 160
[C7x_1 ]   8374.104391 s: [17,6,1] 501: 54
[C7x_1 ]   8374.104403 s: 160
[C7x_1 ]   8374.104412 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104422 s: --------------------------------
[C7x_1 ]   8374.104433 s: 161
[C7x_1 ]   8374.104442 s: [2,7,1] 508: 61
[C7x_1 ]   8374.104455 s: 161
[C7x_1 ]   8374.104465 s: UDMA: ERROR: Data mismatch!!
[C7x_1 ]   8374.104481 s: 162
[C7x_2 ]   8371.367104 s: CIO: Init ... Done !!!
[C7x_2 ]   8371.367123 s: CPU is running FreeRTOS
[C7x_2 ]   8371.367135 s: APP: Init ... !!!
[C7x_2 ]   8372.066686 s: SCICLIENT: Init ... !!!
[C7x_2 ]   8372.066759 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)]
[C7x_2 ]   8372.066785 s: SCICLIENT: DMSC FW revision 0xa
[C7x_2 ]   8372.066806 s: SCICLIENT: DMSC FW ABI revision 4.0
[C7x_2 ]   8372.066826 s: SCICLIENT: Init ... Done !!!
[C7x_2 ]   8372.066849 s: UDMA: Init ... !!!
[C7x_2 ]   8372.066864 s: UDMA: Init ... Done !!!
[C7x_2 ]   8372.066885 s: MEM: Init ... !!!
[C7x_2 ]   8372.066905 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 10a200000 of size 67108864 bytes !!!
[C7x_2 ]   8372.066945 s: MEM: Init ... Done !!!
[C7x_2 ]   8372.066958 s: IPC: Init ... !!!
[C7x_2 ]   8372.066971 s: IPC: 4 CPUs participating in IPC !!!
[C7x_2 ]   8372.067333 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_2 ]   8374.052927 s: IPC: HLOS is ready !!!
[C7x_2 ]   8374.052959 s: appIpcInit: 1003: IPC: RPMessage_announce() for rpmsg-proto success
[C7x_2 ]   8374.053019 s: IPC: Init ... Done !!!
[C7x_2 ]   8374.053035 s: APP: Syncing with 3 CPUs ... !!!
[C7x_2 ]   8374.053070 s: ---------- mv_info: appLogCpuSyncInit:525: slave: C7X_2 id:4 sync with master
[C7x_2 ]   8374.096503 s: ---------- mv_info: appLogCpuSyncInit:527: slave: C7X_2 id:4 sync with master done
[C7x_2 ]   8374.096525 s: APP: Syncing with 3 CPUs ... Done !!!
[C7x_2 ]   8374.096539 s: REMOTE_SERVICE: Init ... !!!
[C7x_2 ]   8374.096649 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_2 ]   8374.096672 s:  VX_ZONE_INIT:Enabled
[C7x_2 ]   8374.096686 s:  VX_ZONE_ERROR:Enabled
[C7x_2 ]   8374.096698 s:  VX_ZONE_WARNING:Enabled
[C7x_2 ]   8374.097402 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2
[C7x_2 ]   8374.097520 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_2
[C7x_2 ]   8374.097630 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_3
[C7x_2 ]   8374.097732 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_4
[C7x_2 ]   8374.097879 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_5
[C7x_2 ]   8374.097987 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_6
[C7x_2 ]   8374.098087 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_7
[C7x_2 ]   8374.098186 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:129] Added target DSP_C7-2_PRI_8
[C7x_2 ]   8374.098213 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
[C7x_2 ]   8374.098232 s: APP: OpenVX Target kernel init ... !!!
[C7x_2 ]   8374.098985 s: motovisC66Version-0518-2:motovis c66 version: 20230215 V1.1.1 match fisheye model v1.14(alg commit 17)
[C7x_2 ]   8374.099139 s: 0528-New C66 to C7x1_2
[C7x_2 ]   8374.099167 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_2 ]   8374.099181 s: APP: Init ... Done !!!
[C7x_2 ]   8374.099192 s: APP: Run ... !!!
[C7x_2 ]   8374.099203 s: IPC: Starting echo test ...
[C7x_2 ]   8374.099321 s: APP: Run ... Done !!!
[C7x_2 ]   8384.099647 s: C7X_2 is running....
[C7x_2 ]   8394.100445 s: C7X_2 is running....
[C7x_2 ]   8404.101244 s: C7X_2 is running....
[C7x_2 ]   8414.102044 s: C7X_2 is running....
[C7x_2 ]   8424.102844 s: C7X_2 is running....
[C7x_2 ]   8434.103644 s: C7X_2 is running....
[C7x_2 ]   8444.104444 s: C7X_2 is running....
^C
root@j722s-evm:~# ^C
root@j722s-evm:~#

Fullscreen testCase.txt Download

int32_t appUdmaTestNDCopy(void)
{
    int32_t                 ret_val = 0;
    uint8_t                *src_buf = NULL, *dest_buf = NULL, *tmp_buf = NULL;
    uint32_t                srcLength,destLength, tmp_length,i,j,z;

    /* set test parameters */
    /* 0..7 UDMA CH, 8..15 DRU CH */
#if defined(C7X_FAMILY)
    uint32_t ch_idx_in = 8;
    uint32_t ch_idx_out = 9;
#else
    uint32_t ch_idx_in = 0;
    uint32_t ch_idx_out = 1;
#endif
    uint32_t padT = 5;
    uint32_t padB = 3;
    uint32_t padL = 2;
    uint32_t padR = 4;


    uint32_t w_blk = 16;
    uint32_t h_blk = 8;
    uint32_t c_blk = 2;
    uint32_t n_blk = 1;
    uint32_t stride_h_blk = w_blk + padL + padR;
    uint32_t stride_c_blk = stride_h_blk * (h_blk + padT + padB); //outChannelPitch
    uint32_t stride_n_blk = stride_c_blk;

    srcLength = stride_n_blk + padT+stride_h_blk+padL;
    destLength = w_blk * h_blk * n_blk;
    tmp_length = destLength;

    /* Allocate buffer memory */
    src_buf = appMemAlloc(APP_UDMA_HEAP_ID, srcLength, APP_UDMA_CACHELINE_ALIGNMENT);
    dest_buf = appMemAlloc(APP_UDMA_HEAP_ID, destLength, APP_UDMA_CACHELINE_ALIGNMENT);
    tmp_buf = appMemAlloc(APP_UDMA_HEAP_ID, tmp_length, APP_UDMA_CACHELINE_ALIGNMENT);
    if((NULL == src_buf) || (NULL == dest_buf) || (NULL == tmp_buf))
    {
        appLogPrintf("UDMA Test: ERROR: mem alloc failed !!!\n");
        ret_val = -1;
    }

    /* make test data */
    if(0 == ret_val)
    {
        /* Init source and dest buffer */
        uint8_t dataNum = 1;
        for(i = 0; i<c_blk; i++)
        {
            for(j = 0; j<h_blk; j++)
            {
                for(z = 0; z<w_blk; z++)
                {
                    src_buf[i*stride_c_blk + (j+padT)*stride_h_blk + padL+z] = dataNum;
                    dest_buf[i*h_blk*w_blk + j*w_blk +z] = 0;
                    dataNum++ ;
                    if(i!= 0)
                        appLogPrintf("[%d,%d,%d] %d: %d\n",padL+z, (j+padT), i, (i*stride_c_blk + (j+padT)*stride_h_blk + padL+z), src_buf[i*stride_c_blk + (j+padT)*stride_h_blk + padL+z]);
                }
            }
        }
        /* Writeback cache */
        appMemCacheWb(src_buf, srcLength);
        appMemCacheWb(dest_buf, destLength);
    }
    /* Do the N-dimentional DMA */
    if(0 == ret_val)
    {
        app_udma_copy_nd_prms_t prms_nd_in;
        app_udma_copy_nd_prms_t prms_nd_out;
        app_udma_ch_handle_t    udmaChIn;
        app_udma_ch_handle_t    udmaChOut;

        appUdmaCopyNDPrms_Init(&prms_nd_in);
        appUdmaCopyNDPrms_Init(&prms_nd_out);

        prms_nd_in.copy_mode    = 3;
        prms_nd_in.src_addr     = appMemGetVirt2PhyBufPtr((uint64_t) &src_buf[padT*stride_h_blk+padL], APP_UDMA_HEAP_ID);
        prms_nd_in.dest_addr    = appMemGetVirt2PhyBufPtr((uint64_t) &tmp_buf[0], APP_UDMA_HEAP_ID);
        prms_nd_in.icnt0        = w_blk;
        prms_nd_in.icnt1        = h_blk;
        prms_nd_in.icnt2        = c_blk;
        prms_nd_in.icnt3        = n_blk;
        prms_nd_in.dim1         = stride_h_blk;
        prms_nd_in.dim2         = stride_c_blk;
        prms_nd_in.dim3         = stride_n_blk;

        prms_nd_in.dicnt0       = prms_nd_in.icnt0;
        prms_nd_in.dicnt1       = prms_nd_in.icnt1;
        prms_nd_in.dicnt2       = prms_nd_in.icnt2; /* Ping-pong */
        prms_nd_in.dicnt3       = prms_nd_in.icnt3;
        prms_nd_in.ddim1        = w_blk;
        prms_nd_in.ddim2        = (h_blk * w_blk);
        prms_nd_in.ddim3        = (h_blk * w_blk * n_blk);

        prms_nd_out.copy_mode   = 3;
        prms_nd_out.src_addr     = appMemGetVirt2PhyBufPtr((uint64_t) &tmp_buf[0], APP_UDMA_HEAP_ID);
        prms_nd_out.dest_addr    = appMemGetVirt2PhyBufPtr((uint64_t) &dest_buf[0], APP_UDMA_HEAP_ID);
        prms_nd_out.icnt0        = w_blk;
        prms_nd_out.icnt1        = h_blk;
        prms_nd_out.icnt2        = c_blk; /* Ping-pong */
        prms_nd_out.icnt3        = n_blk;
        prms_nd_out.dim1         = w_blk;
        prms_nd_out.dim2         = (h_blk * w_blk);
        prms_nd_out.dim3         = (h_blk * w_blk * n_blk);

        prms_nd_out.dicnt0       = prms_nd_out.icnt0;
        prms_nd_out.dicnt1       = prms_nd_out.icnt1;
        prms_nd_out.dicnt2       = prms_nd_out.icnt2;
        prms_nd_out.dicnt3       = prms_nd_out.icnt3;
        prms_nd_out.ddim1        = w_blk;
        prms_nd_out.ddim2        = (h_blk * w_blk);
        prms_nd_out.ddim3        = (h_blk * w_blk * n_blk);

        appLogPrintf("************************ :%d\n",__LINE__);
        appUdmaCopyNDPrmsPrint(&prms_nd_in, "IN");
        appUdmaCopyNDPrmsPrint(&prms_nd_out, "OUT");

        appLogPrintf("************************ :%d\n",__LINE__);
        udmaChIn = appUdmaCopyNDGetHandle(ch_idx_in);
        appLogPrintf("************************ :%d\n",__LINE__);
        udmaChOut = appUdmaCopyNDGetHandle(ch_idx_out);

        appLogPrintf("************************ :%d\n",__LINE__);
        appUdmaCopyNDInit(udmaChIn, &prms_nd_in);
        appUdmaCopyNDInit(udmaChOut, &prms_nd_out);

        appLogPrintf("************************ n_blk:%d\n",n_blk);
        for(i=0; i<n_blk; i++)
        {
            appUdmaCopyNDTrigger(udmaChIn);
            appUdmaCopyNDWait(udmaChIn);
            appUdmaCopyNDTrigger(udmaChOut);
            appUdmaCopyNDWait(udmaChOut);
            appLogPrintf("cur n_blk :%d\n",i);
        }

        appUdmaCopyNDDeinit(udmaChIn);
        appUdmaCopyNDDeinit(udmaChOut);
    }

    /* compare and check test data */
    if(0 == ret_val)
    {
        /* Invalidate cache */
        appMemCacheInv(dest_buf, destLength);

        for( i = 0; i<c_blk; i++)
        {
            appLogPrintf("*********************************************************");
            for(j = 0; j<h_blk; j++)
            {
                appLogPrintf("--------------------------------");
                for( z = 0; z<w_blk; z++)
                {
                    appLogPrintf("%d", dest_buf[i*h_blk*w_blk + j*w_blk +z]);
                    if(src_buf[i*stride_c_blk + (j+padT)*stride_h_blk + padL+z] != dest_buf[i*h_blk*w_blk + j*w_blk +z])
                    {
                        appLogPrintf("[%d,%d,%d] %d: %d\n",padL+z, (j+padT), i, (i*stride_c_blk + (j+padT)*stride_h_blk + padL+z), src_buf[i*stride_c_blk + (j+padT)*stride_h_blk + padL+z]);
                        appLogPrintf("%d    ", dest_buf[i*h_blk*w_blk + j*w_blk +z]);
                        appLogPrintf("UDMA: ERROR: Data mismatch!!\n");
                        ret_val = -1;
                        //break;
                    }
                }
            }
        }
    }

    /* Free buffer memory */
    if(NULL != src_buf)
    {
        appMemFree(APP_UDMA_HEAP_ID, src_buf, srcLength);
        src_buf = NULL;
    }
    if(NULL != dest_buf)
    {
        appMemFree(APP_UDMA_HEAP_ID, dest_buf, destLength);
        dest_buf = NULL;
    }
    if(NULL != tmp_buf)
    {
        appMemFree(APP_UDMA_HEAP_ID, tmp_buf, tmp_length);
        tmp_buf = NULL;
    }

    return (ret_val);
}

0 Rahul Ravikumar 4 months ago in reply to xie jc

TI__Expert 4158 points

Hi Xie jc,

Can you please try removing
appUdmaTest() call from appInit
and try testing the model

This will confirm at least mcu_plus_sdk/dmautils changes are fine

Regards
Rahul T R

0 xie jc 4 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul,

After removing appUdmaTest(), the model can only run one frame and will also get stuck when running the second frame.

Thanks!

0 Jared McArthur 3 months ago in reply to xie jc

TI__Genius 17285 points

Hi Xie Jc,

As Rahul suggested here:

Rahul Ravikumar said:
We don't release some of the TIDL source code, instead we release it as library
And this library depends on dma utils
I guess this library needs rebuild

This feature is part of our 11.0 release which will happen in May mid, I would suggest migration to 11.00 for using this feature

I assume that there is a discrepancy between the TIDL library and the patched dma_utils.

Another possible explanation could be that the model corrupts the DMA cutout and causes the test case to fail.

Best,
Jared

0 Brijesh Jadav 3 months ago in reply to Jared McArthur

TI__Guru**** 476725 points

Hi xie jc,

In the patch that Rahul shared, i see UDMA Test is enabled by calling appUdmaTest API from vision_apps\platform\j722s\rtos\common\app_init.c file. This internally call appUdmaTestNDCopy API, and this API uses index 7 and index 8 for doing ND copy. For Index7, it uses BCDMA channels, but for index 8, it seems to be using DRU channel, based on below condition. So it is using some DRU channels for ND copy operation, can we please disable this test, ie essentially commenting out call to appUdmaTest in vision_apps\platform\j722s\rtos\common\app_init.c file and then try running TIDL?

if(ch_idx>=(APP_UDMA_ND_CHANNELS_MAX/2))
{
udmaCreatePrms.use_dru = 1;
}

Regards,

Brijesh

0 xie jc 3 months ago in reply to Brijesh Jadav

Expert 2180 points

Hi Brijesh,

I understand. You've mentioned it before. Do not use the appUdmaTest API. This has been tried before and the same thing happens when I call TIDL directly, when I run the second frame.

Thanks!

0 Jared McArthur 3 months ago in reply to xie jc

TI__Genius 17285 points

Hi xie jc,

xie jc said:
Attached are log and testCase, when C=2, the source data of the second channel will be tampered with, and there will be a deadlock in accessing the source data.

It appears that your test script isn't even passing. Is the appUdmaTestNDCopy the same as what Rahul sent/patched? It appears different.

Best,
Jared

0 Jared McArthur 3 months ago in reply to Jared McArthur

TI__Genius 17285 points

Hi xie jc,

I've tested a 4D DMA transfer using the DRUs and did not see an issue.

Testcase:

int32_t appUdmaTestNDCopy(void)
{
    int32_t     ret = 0;
    int8_t      test_pass = 0;

    uint32_t    *src_buf = NULL,
                *dest_buf = NULL,
                *tmp_buf = NULL;

    uint32_t    src_len, dest_len, tmp_len;

    uint32_t    line_len, x_stride, y_stride, z_stride;
    uint32_t    x_src_stride, y_src_stride, z_src_stride,
                x_dest_stride, y_dest_stride, z_dest_stride;

    uint32_t    i, x, y, z;
    uint32_t    x_max, y_max, z_max;
    uint32_t    src_offset, src_x_offset, src_y_offset, src_z_offset,
                dest_offset;

    app_udma_copy_nd_prms_t in_prms_nd, out_prms_nd;
    app_udma_ch_handle_t    in_handle_nd, out_handle_nd;

#if defined(C7X_FAMILY)
    uint32_t ch_idx_in = 8;
    uint32_t ch_idx_out = 9;
#else
    uint32_t ch_idx_in = 0;
    uint32_t ch_idx_out = 1;
#endif

    /**
     * Create data of the format:
     * 0:                   [0x0000, 0x0001, 0x0002, 0x0003]
     * x_stride:            [0x0010, 0x0011, 0x0012, 0x0013]
     * 2 * x_stride:        [0x0020, 0x0021, 0x0022, 0x0023]
     * ... cont ...
     * y_stride:            [0x0100, 0x0101, 0x0102, 0x0103]
     * y_stride + x_stride: [0x0110, 0x0111, 0x0112, 0x0113]
     * ... cont ...
     * z_stride:            [0x1000, 0x1001, 0x1002, 0x1003]
     * ... cont ...
     */

    appLogPrintf("UDMA ND Test: test beginning...\n");

    line_len = 4;
    x_max = 3;
    y_max = 5;
    z_max = 10;

    x_stride = 5;
    y_stride = 20;
    z_stride = 120;

    /* strides in units of bytes */
    x_src_stride = sizeof(uint32_t) * x_stride;
    y_src_stride = sizeof(uint32_t) * y_stride;
    z_src_stride = sizeof(uint32_t) * z_stride;

    x_dest_stride = sizeof(uint32_t) * line_len;
    y_dest_stride = x_dest_stride * x_max;
    z_dest_stride = y_dest_stride * y_max;

    /* lengths in units of bytes */
    src_len = z_src_stride * z_max;
    dest_len = z_dest_stride * z_max;
    tmp_len = dest_len;

    src_buf = appMemAlloc(APP_UDMA_HEAP_ID, src_len, APP_UDMA_CACHELINE_ALIGNMENT);
    dest_buf = appMemAlloc(APP_UDMA_HEAP_ID, dest_len, APP_UDMA_CACHELINE_ALIGNMENT);
    tmp_buf = appMemAlloc(APP_UDMA_HEAP_ID, tmp_len, APP_UDMA_CACHELINE_ALIGNMENT);

    if ((src_buf == NULL) || (dest_buf == NULL) || (tmp_buf == NULL)) {
        appLogPrintf("UDMA ND Test: ERROR: memory allocation failed!!!\n");
        ret = -1;
        goto free_buffers;
    }

    appLogPrintf("UDMA ND Test: init buffers...\n");

    /* initialize buffers */
    src_offset = 0;
    src_x_offset = 0;
    src_y_offset = 0;
    src_z_offset = 0;
    dest_offset = 0;
    for (z = 0; z < z_max; ++z) {
        src_z_offset = src_offset;
        for (y = 0; y < y_max; ++y) {
            src_y_offset = src_offset;
            for (x = 0; x < x_max; ++x) {
                src_x_offset = src_offset;
                for (i = 0; i < line_len; ++i) {
                    src_buf[src_offset] = (z << 12) | (y << 8) | (x << 4) | i;
                    dest_buf[dest_offset] = 0;
                    tmp_buf[dest_offset] = 0;
                    src_offset += 1;
                    dest_offset += 1;
                }
                src_offset = src_x_offset + x_stride;
            }
            src_offset = src_y_offset + y_stride;
        }
        src_offset = src_z_offset + z_stride;
    }

    /* writeback cache */
    appMemCacheWb(src_buf, src_len);
    appMemCacheWb(dest_buf, dest_len);

    /* init dma parameters */
    appUdmaCopyNDPrms_Init(&in_prms_nd);

    /* set copy mode */
    in_prms_nd.copy_mode = 0;

    /* set data type */
    /* 4 bytes per element (32 bit uint) */
    in_prms_nd.eltype = 4;

    /* set source data dimensions */
    in_prms_nd.icnt0 = line_len;
    in_prms_nd.icnt1 = x_max;
    in_prms_nd.icnt2 = y_max;
    in_prms_nd.icnt3 = z_max;

    /* set stride dimensions */
    in_prms_nd.dim1 = x_src_stride;
    in_prms_nd.dim2 = y_src_stride;
    in_prms_nd.dim3 = z_src_stride;

    /* set destination data dimensions */
    in_prms_nd.dicnt0 = line_len;
    in_prms_nd.dicnt1 = x_max;
    in_prms_nd.dicnt2 = y_max;
    in_prms_nd.dicnt3 = z_max;

    /* set destination stride dimensions */
    in_prms_nd.ddim1 = x_dest_stride;
    in_prms_nd.ddim2 = y_dest_stride;
    in_prms_nd.ddim3 = z_dest_stride;

    /* set addresses */
    in_prms_nd.src_addr = appMemGetVirt2PhyBufPtr((uint64_t) src_buf, APP_UDMA_HEAP_ID);
    in_prms_nd.dest_addr = appMemGetVirt2PhyBufPtr((uint64_t) tmp_buf, APP_UDMA_HEAP_ID);

    appUdmaCopyNDPrms_Init(&out_prms_nd);

    /* set copy mode */
    out_prms_nd.copy_mode = 0;

    /* set data type */
    /* 4 bytes per element (32 bit uint) */
    out_prms_nd.eltype = 4;

    /* set source data dimensions */
    out_prms_nd.icnt0 = line_len;
    out_prms_nd.icnt1 = x_max;
    out_prms_nd.icnt2 = y_max;
    out_prms_nd.icnt3 = z_max;

    /* set stride dimensions */
    out_prms_nd.dim1 = x_dest_stride;
    out_prms_nd.dim2 = y_dest_stride;
    out_prms_nd.dim3 = z_dest_stride;

    /* set destination data dimensions */
    out_prms_nd.dicnt0 = line_len;
    out_prms_nd.dicnt1 = x_max;
    out_prms_nd.dicnt2 = y_max;
    out_prms_nd.dicnt3 = z_max;

    /* set destination stride dimensions */
    out_prms_nd.ddim1 = x_dest_stride;
    out_prms_nd.ddim2 = y_dest_stride;
    out_prms_nd.ddim3 = z_dest_stride;

    /* set addresses */
    out_prms_nd.src_addr = appMemGetVirt2PhyBufPtr((uint64_t) tmp_buf, APP_UDMA_HEAP_ID);
    out_prms_nd.dest_addr = appMemGetVirt2PhyBufPtr((uint64_t) dest_buf, APP_UDMA_HEAP_ID);

    appLogPrintf("UDMA ND Test: start dma...\n");

    /* init and start dma */
    in_handle_nd = appUdmaCopyNDGetHandle(ch_idx_in);
    out_handle_nd = appUdmaCopyNDGetHandle(ch_idx_out);

    appUdmaCopyNDInit(in_handle_nd, &in_prms_nd);
    appUdmaCopyNDInit(out_handle_nd, &out_prms_nd);

    ret = appUdmaCopyNDTrigger(in_handle_nd);
    if (ret)
        goto deinit_handles;

    ret = appUdmaCopyNDWait(in_handle_nd);
    if (ret)
        goto deinit_handles;

    ret = appUdmaCopyNDTrigger(out_handle_nd);
    if (ret)
        goto deinit_handles;

    ret = appUdmaCopyNDWait(out_handle_nd);
    if (ret)
        goto deinit_handles;

    appUdmaCopyNDDeinit(in_handle_nd);
    appUdmaCopyNDDeinit(out_handle_nd);

    /* Invalidate cache */
    appMemCacheInv(dest_buf, dest_len);

    appLogPrintf("UDMA ND Test: check results...\n");

    /* compare source and destination data */
    src_offset = 0;
    dest_offset = 0;
    for (z = 0; z < z_max; ++z) {
        src_z_offset = src_offset;
        for (y = 0; y < y_max; ++y) {
            src_y_offset = src_offset;
            for (x = 0; x < x_max; ++x) {
                src_x_offset = src_offset;
                for (i = 0; i < line_len; ++i) {
                    if (src_buf[src_offset] != dest_buf[dest_offset]) {
                        appLogPrintf("[%u, %u, %u] %u: DATA MISMATCH: 0x%x != 0x%x\n", z, y, x, i, src_buf[src_offset], dest_buf[dest_offset]);
                        test_pass = -1;
                    }
                    src_offset += 1;
                    dest_offset += 1;
                }
                src_offset = src_x_offset + x_stride;
            }
            src_offset = src_y_offset + y_stride;
        }
        src_offset = src_z_offset + z_stride;
    }

    goto free_buffers;

deinit_handles:
    appUdmaCopyNDDeinit(in_handle_nd);
    appUdmaCopyNDDeinit(out_handle_nd);

free_buffers:
    appLogPrintf("UDMA ND Test: free buffers...\n");

    if (src_buf != NULL)
        appMemFree(APP_UDMA_HEAP_ID, src_buf, src_len);
    if (dest_buf != NULL)
        appMemFree(APP_UDMA_HEAP_ID, dest_buf, dest_len);
    if (tmp_buf != NULL)
        appMemFree(APP_UDMA_HEAP_ID, tmp_buf, dest_len);

    if (test_pass || ret)
        appLogPrintf("UDMA ND Test: test failed!\n");
    else
        appLogPrintf("UDMA ND Test: test passed!\n");

    appLogPrintf("UDMA ND Test: test complete.\n");

    return ret;
}

Log:

[MCU2_0]      5.682455 s: CIO: Init ... Done !!!
[MCU2_0]      5.682494 s: CPU is running FreeRTOS
[MCU2_0]      5.682506 s: APP: Init ... !!!
[MCU2_0]      5.682517 s: SCICLIENT: Init ... !!!
[MCU2_0]      5.682580 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)]
[MCU2_0]      5.682597 s: SCICLIENT: DMSC FW revision 0xa  
[MCU2_0]      5.682610 s: SCICLIENT: DMSC FW ABI revision 4.0
[MCU2_0]      5.682624 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      5.682636 s: UDMA: Init ... !!!
[MCU2_0]      5.682816 s: UDMA: Init ... Done !!!
[MCU2_0]      5.682834 s: MEM: Init ... !!!
[MCU2_0]      5.682847 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ b5800000 of size 33554432 bytes !!!
[MCU2_0]      5.682875 s: MEM: Init ... Done !!!
[MCU2_0]      5.682886 s: IPC: Init ... !!!
[MCU2_0]      5.682900 s: IPC: 4 CPUs participating in IPC !!!
[MCU2_0]      5.683103 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     19.503807 s: IPC: HLOS is ready !!!
[MCU2_0]     19.503871 s: IPC: Init ... Done !!!
[MCU2_0]     19.503887 s: APP: Syncing with 3 CPUs ... !!!
[MCU2_0]     19.503904 s: APP: Syncing with 3 CPUs ... Done !!!
[MCU2_0]     19.503918 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     19.504870 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     19.504943 s: FVID2: Init ... !!!
[MCU2_0]     19.505012 s: FVID2: Init ... Done !!!
[MCU2_0]     19.505493 s: DispApp_init() - DONE !!!
[MCU2_0]     19.516179 s: Display create complete!!
[MCU2_0]     19.516204 s: VHWA: VPAC Init ... !!!
[MCU2_0]     19.516217 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
[MCU2_0]     19.516295 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.516333 s: VHWA: LDC Init ... !!!
[MCU2_0]     19.516433 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     19.516451 s: VHWA: MSC Init ... !!!
[MCU2_0]     19.516979 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     19.516999 s: VHWA: VISS Init ... !!!
[MCU2_0]     19.517685 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     19.517709 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     19.517722 s: VHWA: DMPAC: Init ... !!!
[MCU2_0]     19.517733 s: SCICLIENT: Sciclient_pmSetModuleState module=277 state=2
[MCU2_0]     19.517818 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.517832 s: VHWA: DOF Init ... !!!
[MCU2_0]     19.517942 s: VHWA: DOF Init ... Done !!!
[MCU2_0]     19.517956 s: VHWA: SDE Init ... !!!
[MCU2_0]     19.518031 s: VHWA: SDE Init ... Done !!!
[MCU2_0]     19.518042 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_0]     19.518064 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     19.518077 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     19.518089 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     19.518582 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target MCU2-0 
[MCU2_0]     19.518660 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target VPAC_LDC1 
[MCU2_0]     19.518728 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target VPAC_MSC1 
[MCU2_0]     19.518797 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target VPAC_MSC2 
[MCU2_0]     19.518900 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target VPAC_VISS1 
[MCU2_0]     19.518981 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target CAPTURE1 
[MCU2_0]     19.519049 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target CAPTURE2 
[MCU2_0]     19.519117 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target CAPTURE3 
[MCU2_0]     19.519196 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target CAPTURE4 
[MCU2_0]     19.519264 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DISPLAY1 
[MCU2_0]     19.519335 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DISPLAY2 
[MCU2_0]     19.519403 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target CSITX 
[MCU2_0]     19.519466 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target CSITX2 
[MCU2_0]     19.519526 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DMPAC_SDE 
[MCU2_0]     19.519589 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DMPAC_DOF 
[MCU2_0]     19.519612 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
[MCU2_0]     19.519626 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     19.524443 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     19.524469 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0]     19.524633 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0]     19.524655 s: CSI2RX: Init ... !!!
[MCU2_0]     19.524666 s: SCICLIENT: Sciclient_pmSetModuleState module=182 state=2
[MCU2_0]     19.524706 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.524720 s: SCICLIENT: Sciclient_pmSetModuleState module=247 state=2
[MCU2_0]     19.524772 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.524785 s: SCICLIENT: Sciclient_pmSetModuleState module=185 state=2
[MCU2_0]     19.524828 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.524841 s: SCICLIENT: Sciclient_pmSetModuleState module=251 state=2
[MCU2_0]     19.524881 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.525045 s: CSI2RX: Init ... Done !!!
[MCU2_0]     19.525060 s: CSI2TX: Init ... !!!
[MCU2_0]     19.525071 s: SCICLIENT: Sciclient_pmSetModuleState module=250 state=2
[MCU2_0]     19.525124 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.525136 s: SCICLIENT: Sciclient_pmSetModuleState module=238 state=2
[MCU2_0]     19.525178 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     19.525191 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=250 clk=3 freq=16000000
[MCU2_0]     19.525248 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     19.525261 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=250 clk=4 freq=500000000
[MCU2_0]     19.525312 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     19.525344 s: CSI2TX: Init ... Done !!!
[MCU2_0]     19.525357 s: ISS: Init ... !!!
[MCU2_0]     19.525381 s: IssSensor_Init ... Done !!!
[MCU2_0]     19.525428 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     19.525440 s: ISS: Init ... Done !!!
[MCU2_0]     19.525453 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     19.525494 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     19.525508 s: UDMA Copy: Init ... !!!
[MCU2_0]     19.525774 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     19.525806 s: APP: Init ... Done !!!
[MCU2_0]     19.525822 s: APP: Run ... !!!
[MCU2_0]     19.525833 s: IPC: Starting echo test ...
[MCU2_0]     19.525905 s: APP: Run ... Done !!!
[MCU2_0]     19.526254 s: IPC: Echo status: a530-0[.] main-r5f0-0[s] c75ss0[P] c75ss1[.] 
[MCU2_0]     19.526884 s: IPC: Echo status: a530-0[.] main-r5f0-0[s] c75ss0[P] c75ss1[P] 
[C7x_1 ]      6.004538 s: CIO: Init ... Done !!!
[C7x_1 ]      6.004557 s: CPU is running FreeRTOS
[C7x_1 ]      6.004569 s: APP: Init ... !!!
[C7x_1 ]      6.004578 s: SCICLIENT: Init ... !!!
[C7x_1 ]      6.004637 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)]
[C7x_1 ]      6.004655 s: SCICLIENT: DMSC FW revision 0xa  
[C7x_1 ]      6.004668 s: SCICLIENT: DMSC FW ABI revision 4.0
[C7x_1 ]      6.004680 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      6.004692 s: UDMA: Init ... !!!
[C7x_1 ]      6.004719 s: UDMA: Init ... Done !!!
[C7x_1 ]      6.004733 s: MEM: Init ... !!!
[C7x_1 ]      6.004745 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 117440512 bytes !!!
[C7x_1 ]      6.004770 s: MEM: Init ... Done !!!
[C7x_1 ]      6.004782 s: IPC: Init ... !!!
[C7x_1 ]      6.004796 s: IPC: 4 CPUs participating in IPC !!!
[C7x_1 ]      6.005118 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     18.901080 s: IPC: HLOS is ready !!!
[C7x_1 ]     18.901158 s: IPC: Init ... Done !!!
[C7x_1 ]     18.901172 s: APP: Syncing with 3 CPUs ... !!!
[C7x_1 ]     19.503906 s: APP: Syncing with 3 CPUs ... Done !!!
[C7x_1 ]     19.503924 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     19.504136 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     19.504161 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]     19.504176 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]     19.504196 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]     19.504860 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1 
[C7x_1 ]     19.505014 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     19.505176 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     19.505327 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     19.505477 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     19.505624 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     19.505769 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     19.505920 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     19.505950 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
[C7x_1 ]     19.506010 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     19.506532 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     19.506549 s: APP: Init ... Done !!!
[C7x_1 ]     19.506559 s: APP: UDMA Test !!!
[C7x_1 ]     19.506569 s: UDMA: Test ... !!!
[C7x_1 ]     19.506578 s: UDMA ND Test: test beginning...
[C7x_1 ]     19.506598 s: UDMA ND Test: init buffers...
[C7x_1 ]     19.506617 s: UDMA ND Test: start dma...
[C7x_1 ]     19.506665 s: UDMA : LOG: appUdmaGetClecConfigEvent
[C7x_1 ]     19.506713 s: UDMA : LOG: appUdmaGetClecConfigEvent
[C7x_1 ]     19.506796 s: UDMA ND Test: check results...
[C7x_1 ]     19.506888 s: UDMA ND Test: free buffers...
[C7x_1 ]     19.506904 s: UDMA ND Test: test passed!
[C7x_1 ]     19.506916 s: UDMA ND Test: test complete.
[C7x_1 ]     19.506927 s: UDMA: appUdmaTestNDCopy test passed!!
[C7x_1 ]     19.506968 s: All tests have passed!!
[C7x_1 ]     19.506980 s: UDMA: Test ... Done !!!
[C7x_1 ]     19.506991 s: APP: UDMA Test Done !!!
[C7x_1 ]     19.507001 s: APP: Run ... !!!
[C7x_1 ]     19.507012 s: IPC: Starting echo test ...
[C7x_1 ]     19.507156 s: APP: Run ... Done !!!
[C7x_1 ]     19.526337 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[s] c75ss1[.] 
[C7x_1 ]     19.527064 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[s] c75ss1[P] 
[C7x_2 ]      6.326295 s: CIO: Init ... Done !!!
[C7x_2 ]      6.326312 s: CPU is running FreeRTOS
[C7x_2 ]      6.326324 s: APP: Init ... !!!
[C7x_2 ]      6.326334 s: SCICLIENT: Init ... !!!
[C7x_2 ]      6.326394 s: SCICLIENT: DMSC FW version [10.0.8--v10.00.08 (Fiery Fox)]
[C7x_2 ]      6.326413 s: SCICLIENT: DMSC FW revision 0xa  
[C7x_2 ]      6.326426 s: SCICLIENT: DMSC FW ABI revision 4.0
[C7x_2 ]      6.326440 s: SCICLIENT: Init ... Done !!!
[C7x_2 ]      6.326451 s: UDMA: Init ... !!!
[C7x_2 ]      6.326477 s: UDMA: Init ... Done !!!
[C7x_2 ]      6.326490 s: MEM: Init ... !!!
[C7x_2 ]      6.326502 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 112000000 of size 117440512 bytes !!!
[C7x_2 ]      6.326529 s: MEM: Init ... Done !!!
[C7x_2 ]      6.326541 s: IPC: Init ... !!!
[C7x_2 ]      6.326553 s: IPC: 4 CPUs participating in IPC !!!
[C7x_2 ]      6.326880 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_2 ]     19.110856 s: IPC: HLOS is ready !!!
[C7x_2 ]     19.110933 s: IPC: Init ... Done !!!
[C7x_2 ]     19.110948 s: APP: Syncing with 3 CPUs ... !!!
[C7x_2 ]     19.503906 s: APP: Syncing with 3 CPUs ... Done !!!
[C7x_2 ]     19.503926 s: REMOTE_SERVICE: Init ... !!!
[C7x_2 ]     19.504086 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_2 ]     19.504135 s:  VX_ZONE_INIT:Enabled
[C7x_2 ]     19.504151 s:  VX_ZONE_ERROR:Enabled
[C7x_2 ]     19.504166 s:  VX_ZONE_WARNING:Enabled
[C7x_2 ]     19.505008 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2 
[C7x_2 ]     19.505163 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_2 
[C7x_2 ]     19.505315 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_3 
[C7x_2 ]     19.505462 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_4 
[C7x_2 ]     19.505609 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_5 
[C7x_2 ]     19.505757 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_6 
[C7x_2 ]     19.505917 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_7 
[C7x_2 ]     19.506019 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:124] Added target DSP_C7-2_PRI_8 
[C7x_2 ]     19.506047 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
[C7x_2 ]     19.506063 s: APP: OpenVX Target kernel init ... !!!
[C7x_2 ]     19.506660 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_2 ]     19.506677 s: APP: Init ... Done !!!
[C7x_2 ]     19.506693 s: APP: Run ... !!!
[C7x_2 ]     19.506706 s: IPC: Starting echo test ...
[C7x_2 ]     19.506854 s: APP: Run ... Done !!!
[C7x_2 ]     19.527164 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[.] c75ss1[s] 
[C7x_2 ]     19.527207 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[P] c75ss1[s]

xie jc said:
Synchronizing a message, I also found C7X stuck while verifying the copy of the 3D (WHC) data. And the source data will be tampered with.

I assume there is an issue in the way that you are calculating the addresses for the strides. This doesn't resolve the issue with the model, but it does verify that 4D DMA transfers work properly.

Best,
Jared

0 xie jc 3 months ago in reply to Jared McArthur

Expert 2180 points

Hi Jared,

The 3D DMA copy is also OK. According to the test results, it was blocked because of frequent printing and memory problems before.

Thanks!

0 Jared McArthur 3 months ago in reply to xie jc

TI__Genius 17285 points

Hi Xie Jc,

Does this mean that the TIDL issue is resolved, or just that you've verified DMA copy?

Best,
Jared

0 xie jc 3 months ago in reply to Jared McArthur

Expert 2180 points

Hi Jared,

Only the 3D DMA COPY is verified. The problem with TIDL is that with this patch there is, even if DMA COPY is not called.

Thanks!

0 xie jc 3 months ago in reply to xie jc

Expert 2180 points

Hi Jared，

Regarding the issue mentioned in the email:

TI experts Jared and Rahul started to check the model you shared. In the initial try, they found the model tried to create a tensor with a dimension of 0 and seems not correct. Could you please help to check and feedback any fixes or new model?

Feedback from the engineers who designed the model：

There is no tensor with dimension of 0 in the model. Creating tensors should be an operation carried out in their SDK. We cannot view this.

Thanks！

0 Rahul Ravikumar 3 months ago in reply to xie jc

TI__Expert 4158 points

Hi Xie Jc,

Can you please share the test application used to test the model?
When Jared tried to test the Model Artifacts shared in the email
IO buf descriptor showed the dims for second input as 0

Regards
Rahul T R

0 xie jc 3 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul，

The demo of using the model has been provided in the email, please check.

Thanks!

0 Rahul Ravikumar 3 months ago in reply to xie jc

TI__Expert 4158 points

Hi Xie Jc,

I have not received the email
Can you please check

Regards
Rahul T R

0 xie jc 3 months ago in reply to Rahul Ravikumar

Expert 2180 points

Hi Rahul,

xingyuzhu has helped forward it to you. Please check it.

Thanks!

0 Jared McArthur 2 months ago in reply to xie jc

TI__Genius 17285 points

Hi Xie Jc,

I tried following the instructions within the package but ran into many errors when trying to build perc.out.

$ cd /home/user/ti-processor-sdk-rtos-j722s-evm-10_00_00_05/vision_apps/apps
$ tar -xzvf ~/xxx_demo.tar.gz
$ cd ..
$ make perc
> many errors and failure

I've attached the log to an email (in case it had information that you didn't want posted to the E2E), but I can also share it here if you want.

I also tried to test the network binary and the io descriptor with edgeai-tiovx-apps-test but saw that the second input had a dimension of 0.

Best,
Jared

0 xie jc 2 months ago in reply to Jared McArthur

Expert 2180 points

Hi Jared，

After reading your log, it shows: all warnings being treated as errors.

Please set the compiler to not treat all warnings as errors.

Thanks！

0 Jared McArthur 2 months ago in reply to xie jc

TI__Genius 17285 points

Hi Xie Jc,

Stepping through the code, the application on the A core is waiting for an event to complete on the C7x_1 core.

It appears that there is a fault. Currently trying to find the source.

Best,
Jared

0 xie jc 2 months ago in reply to Jared McArthur

Expert 2180 points

Hi Jared,

How is the analysis of this problem going?

Thanks！

0 Jared McArthur 2 months ago in reply to xie jc

TI__Genius 17285 points

Hi Xie Jc,

The C7x is page faulting due to a virtual address (specifically: 0x000000007EFFFFE0).

I'm currently trying to figure out why the virtual address isn't in the TLB.

Best,
Jared

0 Jared McArthur 2 months ago in reply to Jared McArthur

TI__Genius 17285 points

Hi Xie Jc,

Can you test your model on 11.0?

Otherwise, are you willing to share your model (not just the artifacts), so we can try compiling it on our end?

Best,
Jared

0 xie jc 1 month ago in reply to Jared McArthur

Expert 2180 points

Hi Jared,

Currently, the model team does not have sufficient resources to assist with the model conversion for version 11.0. Please resolve this issue on version 10.0.

There is currently no plan to upgrade to version 11.0 for the project.

Thanks!

0 Jared McArthur 1 month ago in reply to xie jc

TI__Genius 17285 points

Hi Xie Jc,

Is the model team able to send the model over, so we can compile it on our end?

Best,
Jared

Processors

Processors forum

TDA4VEN-Q1: How to use the C7x's DMA in Entry sdk 10.0，update a patch in sdk 10.0