AM6422: AM6422 package pin delay

wang shu

Intellectual 300 points

Part Number: AM6422

Tool/software:

Hi,

May I have the package pin delay for AM6422? I need to do the trace matching from DDR and PCIe.

Best Regards,

Shu

10 months ago

0 Kallikuppa Sreenivasa 10 months ago

TI__Guru**** 191669 points

Hello Shu,

Thank you of the query.

The delay to be considered is the pin-to-pin delay and we have the DDR design guide that could be followed.

Is there a use case for the question.

I will check internally based on your reply.

Regard,

Sreenivasa

0 wang shu 10 months ago in reply to Kallikuppa Sreenivasa

Intellectual 300 points

Hi Sreenivasa,

From the guide, the DQS and DQ skew max delay is 2ps that is 10mils. So I only need to consider the AM6422 ball to LPDDR ball length matching is lesser than 2ps, right? Do I need to consider the internal length mismatch in AM6422 die to ball. Usually we need to include that delay when we do some FPGA design.

Best Regards,

Shu

+1 Kallikuppa Sreenivasa 10 months ago in reply to wang shu

TI__Guru**** 191669 points

Hello Shu,

Thank you for the inputs.

Following the DDR design guide should be Ok. You could also reference the SK and the EVM.

Please refer below inputs from the expert:

we don’t typically share package delay information for the entire device. The customer should be consulting the High Speed Layout Guidelines app note https://www.ti.com/lit/pdf/spraar7 which has layout information for some of the non-DDR interfaces.

For AM64x DDR specifically, the PHY has a per bit skew feature which will compensate for length mismatches during training. This will help accommodate package length mismatches.

Regards,

Sreenivasa

0 wang shu 10 months ago in reply to Kallikuppa Sreenivasa

Intellectual 300 points

Thanks, I will do pin to pin length match.

0 Kallikuppa Sreenivasa 10 months ago in reply to wang shu

TI__Guru**** 191669 points

Hello Shu,

Thank you for the note.

regards,

Sreenivasa

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AM6422: AM6422 package pin delay