Tool/software:
Hi TI's experts,
We are debugging the HLX LPDDR4(32Gb H54G56BYYVX046) in our own TDA4Ven board,there are some failures when I doing the memtester.
Can you help me figure out what the problem is?
memtester result:
Regards.
Tool/software:
Hi TI's experts,
We are debugging the HLX LPDDR4(32Gb H54G56BYYVX046) in our own TDA4Ven board,there are some failures when I doing the memtester.
Can you help me figure out what the problem is?
memtester result:
Regards.
Hi Kevin,
customers change their LPDDR4 from Samsung to skhynix, and they can boot successfully using 3733MHz, but they run the mem test, there is error, so I want help customer enable the read DBI, but it can't work, it will boot fail, can you help customer enable read dbi in TDA4VEN, and can you provide some suggestion to customer?
BR,
Biao
Hi Biao,
When READ DBI is enabled, need to make sure that read latency is also updated. (read latency is dependent on READ DBI setting and DDR clock frequency).
Can you confirm that the read latency is set according to the frequency setting for READ DBI enabled?
Regards,
Kevin
Hi Kevin,
can you help look at this? This is high priority issue, customer previous using samsung, it can't work at high frequency, now Hynix can work on 3733, but there is bit flip issue, we need help customer enable read dbi to have a try at first. or do you have any other suggestion to customer?
BR,
Biao
Hi Kevin,
if you look at the sys file, you will find some mismatch point in DRAM Timing A) Latency Parameters at Operating Frequency sheet:
The Read latency should be 32, but I have let customer try 32, and change other parameter as datasheet (WL,WR) as well, but it can't work. below parameter can work in 3733.
and I enable the dbi based on above parameter. it can't work, so I want to get your support.
BR,
Biao