AM62P: How to change the emmc clock from 200MHz to 195MHz

Hello,

The eMMC can be run at lower speed mode by disabling the higher ones. For example, the following difference makes sure the eMMC is initialized in DDR52.

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index 48898ed15dbd..32b8ca3a01c8 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -621,8 +621,8 @@ sdhci0: mmc@fa10000 {
 		ti,otap-del-sel-legacy = <0x1>;
 		ti,otap-del-sel-mmc-hs = <0x1>;
 		ti,otap-del-sel-ddr52 = <0x6>;
-		ti,otap-del-sel-hs200 = <0x8>;
-		ti,otap-del-sel-hs400 = <0x5>;
+		// ti,otap-del-sel-hs200 = <0x8>;
+		// ti,otap-del-sel-hs400 = <0x5>;
 		ti,itap-del-sel-legacy = <0x10>;
 		ti,itap-del-sel-mmc-hs = <0xa>;
 		ti,itap-del-sel-ddr52 = <0x3>;

Regards,

Prashant

Hi Prashant,

This change only can change to 55MHz, right? but customer want to use 192MHz, they don't want lower down the speed a lot, do you have some guide to them？

BR,

Biao

Hi Biao,

Can the customer try the following patch?

diff --git a/arch/arm/dts/k3-am62p5-sk.dts b/arch/arm/dts/k3-am62p5-sk.dts
index e18c33fead1..e589d8d6dde 100644
--- a/arch/arm/dts/k3-am62p5-sk.dts
+++ b/arch/arm/dts/k3-am62p5-sk.dts
@@ -576,6 +576,7 @@
 &sdhci0 {
 	status = "okay";
 	ti,driver-strength-ohm = <50>;
+    max-frequency = <195000000>;
 	disable-wp;
 	bootph-all;
 };

The corresponding A53 U-Boot logs are:

=> mmc dev 0
switch to partitions #0, OK
mmc0(part 0) is current device
=> mmc info
Device: mmc@fa10000
Manufacturer ID: 13
OEM: 4e
Name: G1M15L
Bus Speed: 195000000
Mode: HS400 (200MHz)

Regards,

Prashant

Hi Prashant,
    According to your suggestion, I have added corresponding modifications in the kernel, using oscilloscope measurements, still at 200MHz.

--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -611,6 +611,7 @@
                clock-names = "clk_ahb", "clk_xin";
                assigned-clocks = <&k3_clks 57 2>;
                assigned-clock-parents = <&k3_clks 57 4>;
+               max-frequency =<192000000>;
                bus-width = <8>;
                mmc-ddr-1_8v;
                mmc-hs200-1_8v;

Hello,

Can you please share the output of the following commands:

=> dmesg | grep mmc
=> cat /sys/kernel/debug/mmc0/ios

Thanks!

Hi Prashant,

    The relevant information is as follows:

Hi Prashant,

can you give some feedback to this？

BR,

Biao

Hi,

After discussing internally, it may not be possible to set the frequency to 192MHz. The feedback is it can possibly be set to a divisor of 200MHz frequency.

Can you help clarify if it is really necessary to use 192MHz? What are the issues with using the original 200MHz?

Thanks!

Hi Prashant,

customers want to change this because of some EMI issue, 200MHz is sensitive frequency point in their system. I think if we can support the frequence around 200MHz, this also can be accepted. 

BR,

Biao 

Hi Prashant:

Because we do not support 192M.

Use sysconfig we found that we can set eMMC clock to 125MHz. work with customer use two method setting it. But use oscilloscope test the clock just run at 100MHz.

Could you please verify it at your side?

Thanks!

Method 1: use below modify at EVM board.

             #K3conf dump clock

                found PLL0 DIV5 do not changed and emmc clock still is 125MHz

+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi

@@ -611,7 +611,10 @@ sdhci0: mmc@fa10000 {

                clock-names = "clk_ahb", "clk_xin";

                assigned-clocks = <&k3_clks 57 2>;

                assigned-clock-parents = <&k3_clks 57 4>;

-               bus-width = <8>;

+               clock-frequency = <125000000>;

+              max-frequency =<125000000>;

Method2: 

#devmem2 0x00680094 w 0x8007

directly change clock tree setting, but use oscilloscope test it eMMC clock change to 100Mhz, do not setting to we wanted 125MHz

Hi Ashwani:

No problem. this problem has been resolved.

Best Regards!

han tao