AM625: SDK10 uboot DDR 4GB

U-Boot SPL 2024.04 (Dec 06 2024 - 14:28:46 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
SPL initial stack usage: 13392 bytes
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024

U-Boot SPL 2024.04 (Dec 06 2024 - 14:30:23 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
SPL initial stack usage: 1904 bytes
Error (-2): cannot determine file size
Trying to boot from MMC2


U-Boot 2024.04 (Dec 06 2024 - 14:30:23 +0800)

SoC:   AM62X SR1.0 GP
Model: Texas Instruments AM625 SK
DRAM:  2 GiB (effective 4 GiB)
Core:  79 devices, 31 uclasses, devicetree: separate
MMC:   mmc@fa10000: 0, mmc@fa00000: 1
Loading Environment from nowhere... OK
In:    serial
Out:   serial
Err:   serial
Net:   eth0: ethernet@8000000port@1
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
Failed to load 'uEnv.txt'
18764288 bytes read in 1576 ms (11.4 MiB/s)
Failed to load '/boot/dtb/ti/k3-am625-sk.dtb'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr <address>" command.
Aborting!
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
Scanning for bootflows in all bootdevs
Seq  Method       State   Uclass    Part  Name                      Filename
---  -----------  ------  --------  ----  ------------------------  ----------------
Scanning global bootmeth 'efi_mgr':
No EFI system partition
No EFI system partition
Failed to persist EFI variables
No EFI system partition
Failed to persist EFI variables
No EFI system partition
Failed to persist EFI variables
No EFI system partition
Failed to persist EFI variables
No EFI system partition
Failed to persist EFI variables
  0  efi_mgr      ready   (none)       0  <NULL>                    
** Booting bootflow '<NULL>' with efi_mgr
Loading Boot0000 'mmc 1' failed
Loading Boot0001 'mmc 0' failed
EFI boot manager: Cannot load any image
Boot failed (err=-14)
Scanning bootdev 'mmc@fa00000.bootdev':
Scanning bootdev 'mmc@fa10000.bootdev':
Bus usb@31100000: generic_phy_get_bulk : no phys property
Register 1000840 NbrPorts 1
Starting the controller
USB XHCI 1.10
scanning bus usb@31100000 for devices... 3 USB Device(s) found
ethernet@8000000port@1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
am65_cpsw_nuss_port ethernet@8000000port@1: phy_startup failed
am65_cpsw_nuss_port ethernet@8000000port@1: am65_cpsw_start end error
ethernet@8000000port@1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
am65_cpsw_nuss_port ethernet@8000000port@1: phy_startup failed
am65_cpsw_nuss_port ethernet@8000000port@1: am65_cpsw_start end error
No more bootdevs
---  -----------  ------  --------  ----  ------------------------  ----------------
(1 bootflow, 1 valid)
=> 
=> 
=> 

// SPDX-License-Identifier: GPL-2.0+
/*
 * Texas Instruments' K3 DDRSS driver
 *
 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <common.h>
#include <config.h>
#include <time.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <fdt_support.h>
#include <ram.h>
#include <hang.h>
#include <log.h>
#include <asm/io.h>
#include <power-domain.h>
#include <wait_bit.h>
#include <power/regulator.h>

#include "lpddr4_obj_if.h"
#include "lpddr4_if.h"
#include "lpddr4_structs_if.h"
#include "lpddr4_ctl_regs.h"

#define SRAM_MAX 512

#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0

#define DDRSS_V2A_CTL_REG			0x0020
#define DDRSS_ECC_CTRL_REG			0x0120

#define DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(x)	((ilog2(x) - 16) << 5)
#define DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK	(~(0x1F << 0x5))
#define DDRSS_V2A_CTL_REG_REGION_IDX_MASK	(~(0X1F))

#define DDRSS_ECC_CTRL_REG_DEFAULT_VAL		0x0
#define DDRSS_ECC_CTRL_REG_ECC_EN		BIT(0)
#define DDRSS_ECC_CTRL_REG_RMW_EN		BIT(1)
#define DDRSS_ECC_CTRL_REG_ECC_CK		BIT(2)
#define DDRSS_ECC_CTRL_REG_WR_ALLOC		BIT(4)

#define DDRSS_ECC_R0_STR_ADDR_REG		0x0130
#define DDRSS_ECC_R0_END_ADDR_REG		0x0134
#define DDRSS_ECC_R1_STR_ADDR_REG		0x0138
#define DDRSS_ECC_R1_END_ADDR_REG		0x013c
#define DDRSS_ECC_R2_STR_ADDR_REG		0x0140
#define DDRSS_ECC_R2_END_ADDR_REG		0x0144
#define DDRSS_ECC_1B_ERR_CNT_REG		0x0150
#define DDRSS_V2A_INT_SET_REG			0x00a8

#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN	BIT(3)
#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN	BIT(4)
#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN	BIT(5)

#define SINGLE_DDR_SUBSYSTEM	0x1
#define MULTI_DDR_SUBSYSTEM	0x2

#define MULTI_DDR_CFG0  0x00114100
#define MULTI_DDR_CFG1  0x00114104
#define DDR_CFG_LOAD    0x00114110

enum intrlv_gran {
	GRAN_128B,
	GRAN_512B,
	GRAN_2KB,
	GRAN_4KB,
	GRAN_16KB,
	GRAN_32KB,
	GRAN_512KB,
	GRAN_1GB,
	GRAN_1_5GB,
	GRAN_2GB,
	GRAN_3GB,
	GRAN_4GB,
	GRAN_6GB,
	GRAN_8GB,
	GRAN_16GB
};

enum intrlv_size {
	SIZE_0,
	SIZE_128MB,
	SIZE_256MB,
	SIZE_512MB,
	SIZE_1GB,
	SIZE_2GB,
	SIZE_3GB,
	SIZE_4GB,
	SIZE_6GB,
	SIZE_8GB,
	SIZE_12GB,
	SIZE_16GB,
	SIZE_32GB
};

struct k3_ddrss_data {
	u32 flags;
};

enum ecc_enable {
	DISABLE_ALL = 0,
	ENABLE_0,
	ENABLE_1,
	ENABLE_ALL
};

enum emif_config {
	INTERLEAVE_ALL = 0,
	SEPR0,
	SEPR1
};

enum emif_active {
	EMIF_0 = 1,
	EMIF_1,
	EMIF_ALL
};

struct k3_msmc {
	enum intrlv_gran gran;
	enum intrlv_size size;
	enum ecc_enable enable;
	enum emif_config config;
	enum emif_active active;
};

#define K3_DDRSS_MAX_ECC_REGIONS		3

struct k3_ddrss_ecc_region {
	u64 start;
	u64 range;
};

struct k3_ddrss_desc {
	struct udevice *dev;
	void __iomem *ddrss_ss_cfg;
	void __iomem *ddrss_ctrl_mmr;
	void __iomem *ddrss_ctl_cfg;
	struct power_domain ddrcfg_pwrdmn;
	struct power_domain ddrdata_pwrdmn;
	struct clk ddr_clk;
	struct clk osc_clk;
	u32 ddr_freq0;
	u32 ddr_freq1;
	u32 ddr_freq2;
	u32 ddr_fhs_cnt;
	u32 dram_class;
	struct udevice *vtt_supply;
	u32 instance;
	lpddr4_obj *driverdt;
	lpddr4_config config;
	lpddr4_privatedata pd;
	struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
	u64 ecc_reserved_space;
	bool ti_ecc_enabled;
	unsigned long long ddr_bank_base[CONFIG_NR_DRAM_BANKS];
	unsigned long long ddr_bank_size[CONFIG_NR_DRAM_BANKS];
	unsigned long long ddr_ram_size;
};

struct reginitdata {
	u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
	u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
	u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
	u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
	u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
	u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
};

#define TH_MACRO_EXP(fld, str) (fld##str)

#define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)

#define str(s) #s
#define xstr(s) str(s)

#define CTL_SHIFT 11
#define PHY_SHIFT 11
#define PI_SHIFT 10

#define DENALI_CTL_0_DRAM_CLASS_DDR4		0xA
#define DENALI_CTL_0_DRAM_CLASS_LPDDR4		0xB

#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
	char *i, *pstr = xstr(REG); offset = 0;\
	for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
		offset = offset * 10 + (*i - '0'); } \
	} while (0)

static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{
	u32 status = 0U;
	u32 offset = 0U;
	u32 regval = 0U;
	u32 dram_class = 0U;
	struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;

	TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
	status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
	if (status > 0U) {
		printf("%s: Failed to read DRAM_CLASS\n", __func__);
		hang();
	}

	dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
		TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
	return dram_class;
}

static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{
	unsigned int req_type, counter;

	for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
		if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
				      CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
				      true, 10000, false)) {
			printf("Timeout during frequency handshake\n");
			hang();
		}

		req_type = readl(ddrss->ddrss_ctrl_mmr +
				 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;

		debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
		      __func__, req_type, counter, ddrss->instance);

		if (req_type == 1)
			clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
		else if (req_type == 2)
			clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
		else if (req_type == 0)
			clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
		else
			printf("%s: Invalid freq request type\n", __func__);

		writel(0x1, ddrss->ddrss_ctrl_mmr +
		       CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
		if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
				      CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
				      false, 10, false)) {
			printf("Timeout during frequency handshake\n");
			hang();
		}
		writel(0x0, ddrss->ddrss_ctrl_mmr +
		       CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
	}
}

static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
	struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;

	debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");

	switch (ddrss->dram_class) {
	case DENALI_CTL_0_DRAM_CLASS_DDR4:
		break;
	case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
		k3_lpddr4_freq_update(ddrss);
		break;
	default:
		printf("Unrecognized dram_class cannot update frequency!\n");
	}
}

static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
{
	int ret;
	lpddr4_privatedata *pd = &ddrss->pd;

	ddrss->dram_class = k3_lpddr4_read_ddr_type(pd);

	switch (ddrss->dram_class) {
	case DENALI_CTL_0_DRAM_CLASS_DDR4:
		/* Set to ddr_freq1 from DT for DDR4 */
		ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
		break;
	case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
		ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
		break;
	default:
		ret = -EINVAL;
		printf("Unrecognized dram_class cannot init frequency!\n");
	}

	if (ret < 0)
		dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
	else
		ret = 0;

	return ret;
}

static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
				   lpddr4_infotype infotype)
{
	if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
		k3_lpddr4_ack_freq_upd_req(pd);
}

static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
{
	int ret;

	debug("%s(ddrss=%p)\n", __func__, ddrss);

	ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
	if (ret) {
		dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
		return ret;
	}

	ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
	if (ret) {
		dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
		return ret;
	}

	ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
					  &ddrss->vtt_supply);
	if (ret) {
		dev_dbg(ddrss->dev, "vtt-supply not found.\n");
	} else {
		ret = regulator_set_value(ddrss->vtt_supply, 3300000);
		if (ret)
			return ret;
		dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
			regulator_get_value(ddrss->vtt_supply));
	}

	return 0;
}

static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
{
	struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
	struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
	void *reg;
	int ret;

	debug("%s(dev=%p)\n", __func__, dev);

	reg = dev_read_addr_name_ptr(dev, "cfg");
	if (!reg) {
		dev_err(dev, "No reg property for DDRSS wrapper logic\n");
		return -EINVAL;
	}
	ddrss->ddrss_ctl_cfg = reg;

	reg = dev_read_addr_name_ptr(dev, "ctrl_mmr_lp4");
	if (!reg) {
		dev_err(dev, "No reg property for CTRL MMR\n");
		return -EINVAL;
	}
	ddrss->ddrss_ctrl_mmr = reg;

	reg = dev_read_addr_name_ptr(dev, "ss_cfg");
	if (!reg)
		dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
	ddrss->ddrss_ss_cfg = reg;

	ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
	if (ret) {
		dev_err(dev, "power_domain_get() failed: %d\n", ret);
		return ret;
	}

	ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
	if (ret) {
		dev_err(dev, "power_domain_get() failed: %d\n", ret);
		return ret;
	}

	ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
	if (ret)
		dev_err(dev, "clk get failed%d\n", ret);

	ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
	if (ret)
		dev_err(dev, "clk get failed for osc clk %d\n", ret);

	/* Reading instance number for multi ddr subystems */
	if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
		ret = dev_read_u32(dev, "instance", &ddrss->instance);
		if (ret) {
			dev_err(dev, "missing instance property");
			return -EINVAL;
		}
	} else {
		ddrss->instance = 0;
	}

	ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0);
	if (ret) {
		ddrss->ddr_freq0 = clk_get_rate(&ddrss->osc_clk);
		dev_dbg(dev,
			"ddr freq0 not populated, using bypass frequency.\n");
	}

	ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
	if (ret)
		dev_err(dev, "ddr freq1 not populated %d\n", ret);

	ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
	if (ret)
		dev_err(dev, "ddr freq2 not populated %d\n", ret);

	ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
	if (ret)
		dev_err(dev, "ddr fhs cnt not populated %d\n", ret);

	ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");

	return ret;
}

void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
{
	u32 status = 0U;
	u16 configsize = 0U;
	lpddr4_config *config = &ddrss->config;

	status = ddrss->driverdt->probe(config, &configsize);

	if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
	    || (configsize > SRAM_MAX)) {
		printf("%s: FAIL\n", __func__);
		hang();
	} else {
		debug("%s: PASS\n", __func__);
	}
}

void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
{
	u32 status = 0U;
	lpddr4_config *config = &ddrss->config;
	lpddr4_obj *driverdt = ddrss->driverdt;
	lpddr4_privatedata *pd = &ddrss->pd;

	if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
		printf("%s: FAIL\n", __func__);
		hang();
	}

	config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctl_cfg;
	config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;

	status = driverdt->init(pd, config);

	/* linking ddr instance to lpddr4  */
	pd->ddr_instance = (void *)ddrss;

	if ((status > 0U) ||
	    (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
	    (pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
	    (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
		printf("%s: FAIL\n", __func__);
		hang();
	} else {
		debug("%s: PASS\n", __func__);
	}
}

void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
				 struct reginitdata *reginit_data)
{
	int ret, i;

	ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
				 (u32 *)reginit_data->ctl_regs,
				 LPDDR4_INTR_CTL_REG_COUNT);
	if (ret)
		printf("Error reading ctrl data %d\n", ret);

	for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
		reginit_data->ctl_regs_offs[i] = i;

	ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
				 (u32 *)reginit_data->pi_regs,
				 LPDDR4_INTR_PHY_INDEP_REG_COUNT);
	if (ret)
		printf("Error reading PI data\n");

	for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
		reginit_data->pi_regs_offs[i] = i;

	ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
				 (u32 *)reginit_data->phy_regs,
				 LPDDR4_INTR_PHY_REG_COUNT);
	if (ret)
		printf("Error reading PHY data %d\n", ret);

	for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
		reginit_data->phy_regs_offs[i] = i;
}

void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
{
	u32 status = 0U;
	struct reginitdata reginitdata;
	lpddr4_obj *driverdt = ddrss->driverdt;
	lpddr4_privatedata *pd = &ddrss->pd;

	populate_data_array_from_dt(ddrss, &reginitdata);

	status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
					  reginitdata.ctl_regs_offs,
					  LPDDR4_INTR_CTL_REG_COUNT);
	if (!status)
		status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
						       reginitdata.pi_regs_offs,
						       LPDDR4_INTR_PHY_INDEP_REG_COUNT);
	if (!status)
		status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
						  reginitdata.phy_regs_offs,
						  LPDDR4_INTR_PHY_REG_COUNT);
	if (status) {
		printf("%s: FAIL\n", __func__);
		hang();
	}
}

void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
{
	u32 status = 0U;
	u32 regval = 0U;
	u32 offset = 0U;
	lpddr4_obj *driverdt = ddrss->driverdt;
	lpddr4_privatedata *pd = &ddrss->pd;

	TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);

	status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
	if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
		printf("%s: Pre start FAIL\n", __func__);
		hang();
	}

	status = driverdt->start(pd);
	if (status > 0U) {
		printf("%s: FAIL\n", __func__);
		hang();
	}

	status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
	if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
		printf("%s: Post start FAIL\n", __func__);
		hang();
	} else {
		debug("%s: Post start PASS\n", __func__);
	}
}

static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size)
{
	writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
	writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
}

#define BIST_MODE_MEM_INIT		4
#define BIST_MEM_INIT_TIMEOUT		10000 /* 1msec loops per block = 10s */
static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss,
					   u64 addr, u64 size,
					   u32 pattern)
{
	lpddr4_obj *driverdt = ddrss->driverdt;
	lpddr4_privatedata *pd = &ddrss->pd;
	u32 status, offset, regval;
	bool int_status;
	int i = 0;

	/* Set BIST_START_ADDR_0 [31:0] */
	regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD));
	TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);

	/* Set BIST_START_ADDR_1 [32 or 34:32] */
	regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD));
	regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD);
	TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);

	/* Set ADDR_SPACE = log2(size) */
	regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD));
	TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);

	/* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a
	 * register with ADDR_SPACE and BIST_GO.
	 */
	TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset);
	driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
	regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
	/* Clear the address check bit */
	TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset);
	driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
	regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);

	/* Set BIST_TEST_MODE[2:0] to memory initialize (4) */
	regval = BIST_MODE_MEM_INIT;
	TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);

	/* Set BIST_DATA_PATTERN[31:0] */
	TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern);

	/* Set BIST_DATA_PATTERN[63:32] */
	TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern);

	udelay(1000);

	/* Enable the programmed BIST operation - BIST_GO = 1 */
	TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset);
	driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
	regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);

	/* Wait for the BIST_DONE interrupt */
	while (i < BIST_MEM_INIT_TIMEOUT) {
		status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE,
						     &int_status);
		if (!status & int_status) {
			/* Clear LPDDR4_INTR_BIST_DONE */
			driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE);
			break;
		}
		udelay(1000);
		i++;
	}

	/* Before continuing we have to stop BIST - BIST_GO = 0 */
	TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset);
	driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0);

	/* Timeout hit while priming the memory. We can't continue,
	 * since the memory is not fully initialized and we most
	 * likely get an uncorrectable error exception while booting.
	 */
	if (i == BIST_MEM_INIT_TIMEOUT) {
		printf("ERROR: Timeout while priming the memory.\n");
		hang();
	}
}

static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss,
					     u64 total_size, u32 pattern)
{
	u32 done, max_size2;

	/* Get the max size (log2) supported in this config (16/32 lpddr4)
	 * from the start_addess width - 16bit: 8G, 32bit: 32G
	 */
	max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) +
		    TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1;

	/* ECC is enabled in dt but we can't preload the memory if
	 * the memory configuration is recognized and supported.
	 */
	if (!total_size || total_size > (1ull << max_size2) ||
	    total_size & (total_size - 1)) {
		printf("ECC: the memory configuration is not supported\n");
		hang();
	}
	printf("ECC is enabled, priming DDR which will take several seconds.\n");
	done = get_timer(0);
	k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern);
	printf("ECC: priming DDR completed in %lu msec\n", get_timer(done));
}

static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss)
{
	int bank, na, ns, len, parent;
	const fdt32_t *ptr, *end;

	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
		ddrss->ddr_bank_base[bank] = 0;
		ddrss->ddr_bank_size[bank] = 0;
	}

	ofnode mem = ofnode_null();

	do {
		mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
	} while (!ofnode_is_enabled(mem));

	const void *fdt = ofnode_to_fdt(mem);
	int node = ofnode_to_offset(mem);
	const char *property = "reg";

	parent = fdt_parent_offset(fdt, node);
	na = fdt_address_cells(fdt, parent);
	ns = fdt_size_cells(fdt, parent);
	ptr = fdt_getprop(fdt, node, property, &len);
	end = ptr + len / sizeof(*ptr);

	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
		if (ptr + na + ns <= end) {
			if (CONFIG_IS_ENABLED(OF_TRANSLATE))
				ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr);
			else
				ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na);

			ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns);
		}

		ptr += na + ns;
	}

	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++)
		ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank];
}

static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss)
{
	u32 v2a_ctl_reg, sdram_idx;

	sdram_idx = DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(ddrss->ddr_ram_size);
	v2a_ctl_reg = readl(ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
	v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK) | sdram_idx;

	if (IS_ENABLED(CONFIG_SOC_K3_AM642))
		v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_REGION_IDX_MASK) | 0xF;

	writel(v2a_ctl_reg, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG);
	writel(DDRSS_ECC_CTRL_REG_DEFAULT_VAL, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
}

static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
{
	fdtdec_setup_mem_size_base_lowest();

	ddrss->ecc_reserved_space = ddrss->ddr_ram_size;
	do_div(ddrss->ecc_reserved_space, 9);

	/* Round to clean number */
	ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space));
}

static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
{
	u64 ecc_region_start = ddrss->ecc_regions[0].start;
	u64 ecc_range = ddrss->ecc_regions[0].range;
	u32 base = (u32)ddrss->ddrss_ss_cfg;
	u32 val;

	/* Only Program region 0 which covers full ddr space */
	k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range);

	/* Enable ECC, RMW, WR_ALLOC */
	writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
	       DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);

	/* Preload the full memory with 0's using the BIST engine of
	 * the LPDDR4 controller.
	 */
	k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0);

	/* Clear Error Count Register */
	writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);

	writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN |
		   DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG);

	/* Enable ECC Check */
	val = readl(base + DDRSS_ECC_CTRL_REG);
	val |= DDRSS_ECC_CTRL_REG_ECC_CK;
	writel(val, base + DDRSS_ECC_CTRL_REG);
}

static int k3_ddrss_probe(struct udevice *dev)
{
	int ret;
	struct k3_ddrss_desc *ddrss = dev_get_priv(dev);

	debug("%s(dev=%p)\n", __func__, dev);

	ret = k3_ddrss_ofdata_to_priv(dev);
	if (ret)
		return ret;

	ddrss->dev = dev;
	ret = k3_ddrss_power_on(ddrss);
	if (ret)
		return ret;

	k3_ddrss_ddr_bank_base_size_calc(ddrss);

	k3_ddrss_ddr_reg_init(ddrss);

	ddrss->driverdt = lpddr4_getinstance();

	k3_lpddr4_probe(ddrss);
	k3_lpddr4_init(ddrss);
	k3_lpddr4_hardware_reg_init(ddrss);

	ret = k3_ddrss_init_freq(ddrss);
	if (ret)
		return ret;

	k3_lpddr4_start(ddrss);

	if (ddrss->ti_ecc_enabled) {
		if (!ddrss->ddrss_ss_cfg) {
			printf("%s: ss_cfg is required if ecc is enabled but not provided.",
			       __func__);
			return -EINVAL;
		}

		k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);

		/* Always configure one region that covers full DDR space */
		ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0];
		ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space;
		k3_ddrss_lpddr4_ecc_init(ddrss);
	}

	return ret;
}

int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
{
	int bank;
	struct k3_ddrss_desc *ddrss = dev_get_priv(dev);

	if (ddrss->ecc_reserved_space == 0)
		return 0;

	for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
		if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) {
			ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank];
			ddrss->ddr_bank_size[bank] = 0;
		} else {
			ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space;
			break;
		}
	}

	return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base,
				      ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS);
}

static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
{
	return 0;
}

static struct ram_ops k3_ddrss_ops = {
	.get_info = k3_ddrss_get_info,
};

static const struct k3_ddrss_data k3_data = {
	.flags = SINGLE_DDR_SUBSYSTEM,
};

static const struct k3_ddrss_data j721s2_data = {
	.flags = MULTI_DDR_SUBSYSTEM,
};

static const struct udevice_id k3_ddrss_ids[] = {
	{.compatible = "ti,am62a-ddrss", .data = (ulong)&k3_data, },
	{.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
	{.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
	{.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
	{}
};

U_BOOT_DRIVER(k3_ddrss) = {
	.name			= "k3_ddrss",
	.id			= UCLASS_RAM,
	.of_match		= k3_ddrss_ids,
	.ops			= &k3_ddrss_ops,
	.probe			= k3_ddrss_probe,
	.priv_auto		= sizeof(struct k3_ddrss_desc),
};

static int k3_msmc_set_config(struct k3_msmc *msmc)
{
	u32 ddr_cfg0 = 0;
	u32 ddr_cfg1 = 0;

	ddr_cfg0 |= msmc->gran << 24;
	ddr_cfg0 |= msmc->size << 16;
	/* heartbeat_per, bit[4:0] setting to 3 is advisable */
	ddr_cfg0 |= 3;

	/* Program MULTI_DDR_CFG0 */
	writel(ddr_cfg0, MULTI_DDR_CFG0);

	ddr_cfg1 |= msmc->enable << 16;
	ddr_cfg1 |= msmc->config << 8;
	ddr_cfg1 |= msmc->active;

	/* Program MULTI_DDR_CFG1 */
	writel(ddr_cfg1, MULTI_DDR_CFG1);

	/* Program DDR_CFG_LOAD */
	writel(0x60000000, DDR_CFG_LOAD);

	return 0;
}

static int k3_msmc_probe(struct udevice *dev)
{
	struct k3_msmc *msmc = dev_get_priv(dev);
	int ret = 0;

	/* Read the granular size from DT */
	ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran);
	if (ret) {
		dev_err(dev, "missing intrlv-gran property");
		return -EINVAL;
	}

	/* Read the interleave region from DT */
	ret = dev_read_u32(dev, "intrlv-size", &msmc->size);
	if (ret) {
		dev_err(dev, "missing intrlv-size property");
		return -EINVAL;
	}

	/* Read ECC enable config */
	ret = dev_read_u32(dev, "ecc-enable", &msmc->enable);
	if (ret) {
		dev_err(dev, "missing ecc-enable property");
		return -EINVAL;
	}

	/* Read EMIF configuration */
	ret = dev_read_u32(dev, "emif-config", &msmc->config);
	if (ret) {
		dev_err(dev, "missing emif-config property");
		return -EINVAL;
	}

	/* Read EMIF active */
	ret = dev_read_u32(dev, "emif-active", &msmc->active);
	if (ret) {
		dev_err(dev, "missing emif-active property");
		return -EINVAL;
	}

	ret = k3_msmc_set_config(msmc);
	if (ret) {
		dev_err(dev, "error setting msmc config");
		return -EINVAL;
	}

	return 0;
}

static const struct udevice_id k3_msmc_ids[] = {
	{ .compatible = "ti,j721s2-msmc"},
	{}
};

U_BOOT_DRIVER(k3_msmc) = {
	.name = "k3_msmc",
	.of_match = k3_msmc_ids,
	.id = UCLASS_MISC,
	.probe = k3_msmc_probe,
	.priv_auto = sizeof(struct k3_msmc),
	.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
};

[BEGIN] 2024/12/6 15:21:15

U-Boot SPL 2024.04 (Dec 06 2024 - 14:28:46 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
SPL initial stack usage: 13392 bytes
Trying to boot from MMC2
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b87-dirty
NOTICE:  BL31: Built : 16:09:05, Feb  9 2024

U-Boot SPL 2024.04 (Dec 06 2024 - 14:30:23 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
SPL initial stack usage: 1904 bytes
Error (-2): cannot determine file size
Trying to boot from MMC2


U-Boot 2024.04 (Dec 06 2024 - 14:30:23 +0800)

SoC:   AM62X SR1.0 GP
Model: Texas Instruments AM625 SK
DRAM:  2 GiB (effective 4 GiB)
Core:  79 devices, 31 uclasses, devicetree: separate
MMC:   mmc@fa10000: 0, mmc@fa00000: 1
Loading Environment from nowhere... OK
In:    serial
Out:   serial
Err:   serial
Net:   eth0: ethernet@8000000port@1
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
Failed to load 'uEnv.txt'
18764288 bytes read in 1575 ms (11.4 MiB/s)
60191 bytes read in 27 ms (2.1 MiB/s)
Working FDT set to 88000000
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
Working FDT set to 88000000
   Loading Device Tree to 000000008feee000, end 000000008fffffff ... OK
Working FDT set to 8feee000

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
re 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Wed Mar 15 14:09:56 CST 2023
[    0.000000] Machine model: Texas Instruments AM625 SK
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x00000000f8000000, size 128 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x000000009c800000, size 3 MiB
[    0.000000] OF: reserved mem: initialized node ipc-memories@9c800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x000000009cb00000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node m4f-dma-memory@9cb00000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x000000009cc00000, size 14 MiB
[    0.000000] OF: reserved mem: initialized node m4f-memory@9cc00000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x000000009da00000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@9da00000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x000000009db00000, size 12 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@9db00000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   empty
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000008007ffff]
[    0.000000]   node   0: [mem 0x0000000080080000-0x000000009c7fffff]
[    0.000000]   node   0: [mem 0x000000009c800000-0x000000009e6fffff]
[    0.000000]   node   0: [mem 0x000000009e700000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x000000009fffffff]
[    0.000000]   node   0: [mem 0x00000000a0000000-0x00000000ffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000] On node 0 totalpages: 524288
[    0.000000]   DMA zone: 8192 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 524288 pages, LIFO batch:63
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 18 pages/cpu s33496 r8192 d32040 u73728
[    0.000000] pcpu-alloc: s33496 r8192 d32040 u73728 alloc=18*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 516096
tfs),256k@130816k(ospi_nand.phypattern) root=PARTUUID=0f41e470-02 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
112K reserved, 131072K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu: 	RCU event tracing is enabled.
[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4.
[    0.000000] 	Trampoline variant of Tasks RCU enabled.
[    0.000000] 	Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 256 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] GICv3: Distributor has no Range Selector support
[    0.000000] GICv3: 16 PPIs implemented
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001880000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @80c00000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x0000000080430000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000080440000
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000001] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.008549] Console: colour dummy device 80x25
[    0.013143] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.023825] pid_max: default: 32768 minimum: 301
[    0.028633] LSM: Security Framework initializing
[    0.033416] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[    0.040998] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[    0.050830] rcu: Hierarchical SRCU implementation.
[    0.056023] Platform MSI: msi-controller@1820000 domain created
[    0.062351] PCI/MSI: /bus@f0000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.071624] EFI services will not be available.
[    0.076539] smp: Bringing up secondary CPUs ...
[    0.081813] Detected VIPT I-cache on CPU1
[    0.085945] GICv3: CPU1: found redistributor 1 region 0:0x00000000018a0000
[    0.092983] GICv3: CPU1: using allocated LPI pending table @0x0000000080450000
[    0.100420] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.107754] Detected VIPT I-cache on CPU2
[    0.111873] GICv3: CPU2: found redistributor 2 region 0:0x00000000018c0000
[    0.118907] GICv3: CPU2: using allocated LPI pending table @0x0000000080460000
[    0.126321] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.133661] Detected VIPT I-cache on CPU3
[    0.137779] GICv3: CPU3: found redistributor 3 region 0:0x00000000018e0000
[    0.144813] GICv3: CPU3: using allocated LPI pending table @0x0000000080470000
[    0.152225] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.158976] smp: Brought up 1 node, 4 CPUs
[    0.163182] SMP: Total of 4 processors activated.
[    0.167996] CPU features: detected: 32-bit EL0 Support
[    0.173262] CPU features: detected: CRC32 instructions
[    0.185837] CPU: All CPU(s) started at EL2
[    0.190045] alternatives: patching kernel code
[    0.195589] devtmpfs: initialized
[    0.206596] KASLR disabled due to lack of seed
[    0.211313] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.221292] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[    0.232140] pinctrl core: initialized pinctrl subsystem
[    0.238146] DMI not present or invalid.
[    0.242767] NET: Registered protocol family 16
[    0.249023] DMA: preallocated 256 KiB GFP_KERNEL pool for atomic allocations
[    0.256381] DMA: preallocated 256 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.264452] DMA: preallocated 256 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.273167] thermal_sys: Registered thermal governor 'step_wise'
[    0.273765] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.286963] ASID allocator initialised with 65536 entries
[    0.316987] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.323872] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.330753] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.337609] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.345457] cryptd: max_cpu_qlen set to 1000
[    0.352639] k3-chipinfo 43000014.chipid: Family:AM62X rev:SR1.0 JTAGID[0x0bb7e02f] Detected
[    0.361694] vcc_5v0: supplied by vmain_pd
[    0.366242] vcc_3v3_sys: supplied by vmain_pd
[    0.371084] vcc_1v8: supplied by vcc_3v3_sys
[    0.376410] iommu: Default domain type: Translated 
[    0.381750] SCSI subsystem initialized
[    0.386002] mc: Linux media interface: v0.10
[    0.390391] videodev: Linux video capture interface: v2.00
[    0.396082] pps_core: LinuxPPS API ver. 1 registered
[    0.401159] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.410513] PTP clock support registered
[    0.414553] EDAC MC: Ver: 3.0.0
[    0.418421] omap-mailbox 29000000.mailbox: omap mailbox rev 0x66fc9100
[    0.425554] FPGA manager framework
[    0.429119] Advanced Linux Sound Architecture Driver Initialized.
[    0.436272] clocksource: Switched to clocksource arch_sys_counter
[    0.442732] VFS: Disk quotas dquot_6.6.0
[    0.446799] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.459243] NET: Registered protocol family 2
[    0.463991] IP idents hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.472812] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
[    0.481604] TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
[    0.489813] TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
[    0.497536] TCP: Hash tables configured (established 16384 bind 16384)
[    0.504438] UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
[    0.511342] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
[    0.518847] NET: Registered protocol family 1
[    0.523772] RPC: Registered named UNIX socket transport module.
[    0.529846] RPC: Registered udp transport module.
[    0.534656] RPC: Registered tcp transport module.
[    0.539463] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.546052] NET: Registered protocol family 44
[    0.550610] PCI: CLS 0 bytes, default 64
[    0.555471] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[    0.567478] Initialise system trusted keyrings
[    0.572284] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    0.582528] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.589086] NFS: Registering the id_resolver key type
[    0.594302] Key type id_resolver registered
[    0.598582] Key type id_legacy registered
[    0.602743] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.609599] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.617376] 9p: Installing v9fs 9p2000 file system support
[    0.658945] Key type asymmetric registered
[    0.663143] Asymmetric key parser 'x509' registered
[    0.668170] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
[    0.675738] io scheduler mq-deadline registered
[    0.680376] io scheduler kyber registered
[    0.685704] phy-gmii-sel 104044.phy: Failed to get syscon -22
[    0.691611] phy-gmii-sel: probe of 104044.phy failed with error -22
[    0.698519] pinctrl-single 4084000.pinctrl: 34 pins, size 136
[    0.704886] pinctrl-single f4000.pinctrl: initialized with no interrupts
[    0.711749] pinctrl-single f4000.pinctrl: 171 pins, size 684
[    0.718519] pinctrl-single a40000.pinctrl: 512 pins, size 2048
[    0.727556] ti-syscon-gate-clk 104130.clock-controller: failed to find parent regmap
[    0.735526] ti-syscon-gate-clk: probe of 104130.clock-controller failed with error -22
[    0.747953] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[    0.767655] brd: module loaded
[    0.777855] loop: module loaded
[    0.781966] megasas: 07.714.04.00-rc1
[    0.789252] tun: Universal TUN/TAP device driver, 1.6
[    0.794999] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    0.801423] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    0.807533] sky2: driver version 1.30
[    0.812199] VFIO - User Level meta-driver version: 0.3
[    0.818472] i2c /dev entries driver
[    0.823768] sdhci: Secure Digital Host Controller Interface driver
[    0.830119] sdhci: Copyright(c) Pierre Ossman
[    0.834886] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.841943] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    0.850084] optee: probing for conduit method.
[    0.854696] optee: revision 4.2 (12d7c4ee)
[    0.854984] optee: dynamic shared memory is enabled
[    0.864582] optee: initialized driver
[    0.870357] NET: Registered protocol family 17
[    0.875081] 9pnet: Installing 9P2000 support
[    0.879535] Key type dns_resolver registered
[    0.884315] printk: bootconsole [ns16550a0]: printing thread started
[    0.884361] Loading compiled-in X.509 certificates
[    0.893048] ti-sci 44043000.system-controller: lpm region is required for suspend but not provided.
[    0.893103] ti-sci 44043000.system-controller: ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
[    0.908376] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=13, clk=7, ret=-19
[    0.910062] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=36, clk=9, ret=-19
[    0.910692] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=36, clk=15, ret=-19
[    0.910788] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=36, clk=16, ret=-19
[    0.910910] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=36, clk=17, ret=-19
[    0.911009] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=36, clk=18, ret=-19
[    0.912043] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=37, clk=9, ret=-19
[    0.979164] printk: console [ttyS2]: printing thread started
[    0.912702] ti-sci-clk 44043000.system-controller:clock-controller: recalc-rate failed for dev=37, clk=15, ret=-19
[    0.979179] printk: console [ttyS2] enabled
[    0.979183] printk: bootconsole [ns16550a0] disabled
[    1.005918] printk: bootconsole [ns16550a0]: printing thread stopped
[    1.010367] spi-nor spi0.0: s28hs512t (65536 Kbytes)
[    1.010433] 7 fixed-partitions partitions found on MTD device fc40000.spi.0
[    1.010438] Creating 7 MTD partitions on "fc40000.spi.0":
[    1.010445] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    1.011683] 0x000000080000-0x000000280000 : "ospi.tispl"
[    1.012710] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    1.013692] 0x000000680000-0x0000006c0000 : "ospi.env"
[    1.014680] 0x0000006c0000-0x000000700000 : "ospi.env.backup"
[    1.015637] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    1.016629] 0x000003fc0000-0x000004000000 : "ospi.phypattern"
[    1.019582] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.056273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.058388] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.058402] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.060956] rtc-ti-k3 2b1f0000.rtc: registered as rtc0
[    1.065799] rtc-ti-k3 2b1f0000.rtc: setting system clock to 1970-01-01T00:00:07 UTC (7)
[    1.066555] k3-j72xx-soc-thermal b00000.temperature-sensor: invalid resource
[    1.066588] k3-j72xx-soc-thermal: probe of b00000.temperature-sensor failed with error -22
[    1.067878] cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 1200000 KHz, changing to: 1250000 KHz
[    1.070019] mmc0: CQHCI version 5.10
[    1.070283] davinci-mcasp 2b10000.audio-controller: IRQ common not found
[    1.079905] pca953x 1-0022: supply vcc not found, using dummy regulator
[    1.080037] pca953x 1-0022: using AI
[    1.100398] pca953x 1-0022: failed writing register
[    1.100532] pca953x: probe of 1-0022 failed with error -121
[    1.102979] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.108300] mmc0: SDHCI controller on fa10000.mmc [fa10000.mmc] using ADMA 64-bit
[    1.144277] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.146227] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.146240] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.150805] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.187385] mmc0: Command Queue Engine enabled
[    1.187403] mmc0: new HS200 MMC card at address 0001
[    1.188049] mmcblk0: mmc0:0001 S0J56X 14.8 GiB 
[    1.188230] mmcblk0boot0: mmc0:0001 S0J56X partition 1 31.5 MiB
[    1.188338] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.188435] mmcblk0boot1: mmc0:0001 S0J56X partition 2 31.5 MiB
[    1.188612] mmcblk0rpmb: mmc0:0001 S0J56X partition 3 4.00 MiB, chardev (237:0)
[    1.189949]  mmcblk0: p1 p2
[    1.190715] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.190729] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.195722] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.236272] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.238149] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.238161] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.242286] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.284274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.286139] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.286150] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.290324] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.328279] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.330202] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.330216] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.334384] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.376274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.378153] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.378166] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.382310] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.420274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.422151] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.422162] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.426326] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.468283] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.470167] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.470179] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.474331] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.516274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.518152] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.518164] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.522331] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.560271] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.562154] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.562166] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.566314] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.608274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.610157] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.610169] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.614281] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.652283] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.654144] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.654158] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.658320] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.700276] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.702156] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.702168] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.706309] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.748273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.750138] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.750151] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.754310] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.792271] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.794147] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.794159] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.798328] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.840273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.842157] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.842169] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.846361] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.888381] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.890256] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.890270] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.894473] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.936272] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.938144] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.938156] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.942331] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.980270] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.982146] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.982159] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    1.986309] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.028274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.030137] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.030150] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.034348] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.076279] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.078147] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.078159] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.082318] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.124277] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.126145] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.126157] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.130372] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.172273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.174145] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.174157] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.178398] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.216270] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.218163] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.218175] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.222360] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.264275] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.266143] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.266155] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.270311] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.312273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.314155] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.314166] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.318303] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.360274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.362156] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.362168] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.366398] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.408273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.410154] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.410164] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.414325] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.456408] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.458262] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.458275] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.462463] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.504280] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.506173] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.506185] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.510378] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.548270] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.550146] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.550159] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.554345] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.592272] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.594123] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.594136] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.598357] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.640273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.642148] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.642159] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.646326] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.688382] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.690250] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.690263] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.694462] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.736273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.738159] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.738171] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.742354] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.784273] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.786163] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.786175] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.790341] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.828278] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.830147] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.830159] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.834361] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.876293] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.878171] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.878184] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.882376] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.924275] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.926145] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.926158] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517
[    2.930390] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    2.972274] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.974147] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    2.974160] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
: 3 quirks:00000006
-517

[END] 2024/12/6 15:25:37