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Original question:

AM6442: Synchronize or start timers at the same time to generate precisely timed outputs on TIMER_IO pins.

AM6442: Timer in one shot compare mode not working as expected

Stefan Glaser2
Prodigy 140 points
Part Number: AM6442

Tool/software:

Hello,

I am trying to get the timer working in one shot mode in combination with compare mode. Here is the register configuration of Timer6:

What I would expect to happen is that the timer output pin will get set high at the compare value and set low again at overflow (or stay high) and then the timer should stop.
What is happening instead is that the output is set high for exactly two clock cycles and then back to low and then the timer stops (ST bit is 0).
If I set the the PT bit to 0 I get a high at the output for exactly one clock cycle.

Why is the compare mode not working?
Why is the output in one shot mode (AR bit is 0) high for two clock cycles independent of basically any of the registers.

If I set the reload register and enable autor-reload (AR = 1) the PWM generation is working as expected.

What am I doing wrong in one shot mode?

Thank you!
Greetings
Stefan

  • 0
    TI__Guru**** 168261 points

    Hi Stefan,

    Is this in Linux or RTOS?

  • 0 in reply to Bin Liu
    Prodigy 140 points

    No RTOS, bare metal on R5F.
    I realized that compare is also not triggering the first time in auto reload mode, just the second time.

    Thank you!
    Greetings

  • 0 in reply to Stefan Glaser2
    TI__Guru**** 168261 points

    I am routing your query to our Timer expert for comments.

  • 0 in reply to Bin Liu
    TI__Mastermind 46436 points

    Hello Stefen,

    Stefan Glaser2 said:
    What I would expect to happen is that the timer output pin will get set high at the compare value and set low again at overflow (or stay high) and then the timer should stop.

    Based on the above comments, you are expecting the highlighted solution below.

    Then you need to enable the TRG mode for both compare and overflow with SCPWM bit = 1.

    Please, look at the FAQ below which is helpful driving the PWM from the timer module.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1377521/faq-processor-sdk-am64x-how-to-create-a-pwm-using-a-timer

    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    Prodigy 140 points

    Hello,

    Thank you for your reply! Everything you described is working as expected.

    But that is not the issue. The issue is that the match pulse is not triggering the first time when the timer is starting from zero or below the match value. The match pulse is only ever triggering if there was an overflow before. This also means that the match pulse is never triggering in one-shot mode. Is this the intended behavior?

    In the pictures you provided above there is also always an overflow pulse before a match pulse.

    Thank you!
    Greetings,
    Stefan

  • 0 in reply to Stefan Glaser2
    TI__Mastermind 46436 points

    Hello Stefen,

    The match pulse is triggered when the counter matches to matched register value and in all other cases the match pulse will not trigger.

    The match pulse will trigger in one shot mode as well.

    The counter first starts from 0 till the maximum count value . In this case, based on the match register value, first match pulse triggers and later overflow pulse triggers. In one shot mode, at least you should get the one match pulse and one overflow pulse.

    Regards,

    Anil.

  • 0 in reply to Swargam Anil
    Prodigy 140 points

    Hello,

    Again thank you for your reply!

    What you described now is exactly what I would expect. I can recreate everything described in the datasheet and get all the wave-forms shown there so I think I have a fairly good understanding by now of how to configure the timer. But I tried all imaginable register setting combinations and I can not get the match pulse to trigger the first time without an overflow before.

    Did you try to get a match pulse without an overflow first (or in singe shot mode) on the AM6442 and can 100% confirm that it works?

    Thank you!

  • 0 in reply to Stefan Glaser2
    TI__Mastermind 46436 points

    Hello Stefen,

    Please look at the above FAQ and in that example I have already followed the same method.

    I am controlling duty and frequency with the match and overflow registers .

    For example, the TLDR register is loaded with 0x00, so, the TCRR starts from 0x00.

    Next, when ever TCRR register matches the TMAR Register , then it triggers one Match pulse and finally the counter overflows at 32 bit value here overflow pulse is triggers.

    These values are mainly based on which values you are feeding to TMAR registers and TLDR registers.

    Please check the FAQ above . You get an idea and, in the example, I enabled AR mode . Here, you can change to One shot mode.

    Regards,

    Anil.