PROCESSOR-SDK-AM62X: Low Power Mode use and Security in Wakeup Sources

Is there additional resources you could point me towards that would help better in understanding what SYSFW is doing to make this work?  Specifically I'm trying to follow up on understanding how this works in Partial I/O mode given the rest of the SoC is turned off but the CANUART I/O bank helps the software distinguish between a cold boot and a wake up event.

Hi Wayne,

I am routing your query to our Low Power Mode expert for comments.

Hi Wayne,

To start with SYSFW, refer to the TISCI documentation: https://downloads.ti.com/tisci/esd/latest/1_intro/TISCI.html

For AM62x specific information, see the SoC specific section: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/index.html

For a generic Low Power Mode sequence, refer to the Linux SDK documentation: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/10_00_07_04/exports/docs/linux/Foundational_Components/Power_Management/pm_sw_arch.html

The DM R5 in the diagram is running the SYSFW.

To my understanding in Partial I/O mode, the DDR is not put in self-refresh, so the TIFS won't write its content from SRAM to DDR. I'll check again internally on this.

Partial I/O mode will only keep a select number of pins and some SoC logic online because the PMIC will supply power to the CANUART domain.

The only difference between cold boot and a wakeup event in Partial I/O mode is what IO triggers this resume sequence. A cold boot would most likely trigger after a reset signal to the SoC rather Partial I/O mode would wakeup after a edge change on an IO which might be driven by an external module. Waking up from Partial I/O will start a cold boot sequence.

Best Regards,

Anshu

Hi Wayne,

Just to confirm, the TIFS core will not write its SRAM to DDR for Partial I/O Mode.

Thanks,

Anshu

Anshu, I think the confusion is coming from trying to understand what you said in comparison to what is written in the Tech Ref Manual.  Specifically on section 6.2.4.5 Partial I/O, the paragraph ends with "The information on the I/O wakeup event is logged in the MMR in the CANUART I/O bank and helps the software to distinguish between cold boot and wakeup to respond to the wakeup event faster."

The statement that SRAM isn't stored in DDR for Partial I/O does make sense in that the SoC is in a power off state.  However, I don't understand how the system would be able to respond to the wake up event faster if a wake up trigger from a partial i/o will just process a cold boot sequence.  Wouldn't that be equally responsive as they are both cold boot sequences?

In the TRM, section 6.2.4.10 Low Power Mode Sequencing with Device Manager discusses the steps used to go into a low power mode, including the TISCI_MSG_PREPARE_SLEEP message.  Looking then into the TISCI documentation that you linked, this message contains contexts for high/low addresses to save which seems to correlate to the encrypted content saved during deep sleep mode.  Does SYSFW just not set those values during a Partial I/O low power mode?

Ignore the last question around TISCI_MSG_PREPARE_SLEEP.  I found my answer in the TISCI documentation with a comment under the message definition section. "Mode parameter should be equal to partial IO low power mode for partial IO mode entry. In this mode, ctx_lo and ctx_hi are unused. There is no requirement of “carve out” in DDR."

I haven't found an answer on the responding to a wake up event faster yet though.

Hi Wayne,

Wayne Bogart said:

"The information on the I/O wakeup event is logged in the MMR in the CANUART I/O bank and helps the software to distinguish between cold boot and wakeup to respond to the wakeup event faster."

Let me check with the design team on this internally. Please ping this thread if you haven't received a response by Monday.

Best Regards,

Anshu

Hello Anshu.  Pinging a reminder as requested.

Hi Wayne,

Thank you for the reminder. After discussing internally, there isn't really a difference between a cold boot and Partial I/O mode so there isn't much time saved for using Partial I/O mode. One of the benefits is the wakeup can be driven by SoC IOs rather than using an application shutdown or a power cycle to cold boot the SoC, but this wouldn't significantly impact the time to trigger a wakeup.

Best Regards,

Anshu