PROCESSOR-SDK-J784S4: ISR Configuration for CddIpc on configtool

Hello,

 Currently we have CDD IPC Interrupt configuration being done as part of application ,in mcusw/mcal_drv/mcal/examples/CddIpc/soc/j784s4/mcu1_0/CddIpcAppStartup.c path at 

Hi Tarun, 

Not sure if dont have same context but I didnt understand pretty well your reply, I continue checking configuration and documentation. What I have not is that at some point ISR needs to be added on OS component and mapped to a source expected by CddIpc, from CddIpc perspective I have that CAT2 ISR is configured as below:

However, inside CddIpc module I cannot create any ISR or something similar, just specify ISR type, on the other hand, if I try to add and ISR on OS module I am seeing something like this:

So, at this point I am thinking to match OS ISR with the one expected in CddIpc to receive new mailbox data is to set properly Interrupt Source, I was navigating into Technical Reference, and I am wondering if I must refer to interrupt ID 44 and 45 since are the ones referred to R5F core.

At this point and summarizing I am just trying to configure properly CddIpc (it is already generating code individually) but my concern is when I try to configure corresponding ISR so my notification callback will be called properly.

Hello,

Since you are using CAT2 interrupt , the ISR is synonymous with Interrupt. In the case of Cat1 interrupt the Interrupt handler is the function.

You need to configure the Interrupt source number in your AUTOSAR OS configurator. The interrupt source number will be based on which two cores your communication is happening and to which core it is happening.

Between which cores is your communication happening ?

Regards

Tarun Mukesh

Communication we are trying to establish is between MCU and MPU1_0, remote core is MPU1_0 and host is MCU1_0.

Hello,

We have a cdd ipc example between MCU1_0 and A72 core.

Interrupt routing is done from MPU1_0 to MCU1_0

+ rmIrqRel.src_id = TISCI_DEV_NAVSS0_MAILBOX_0;
+ rmIrqRel.src_index = 1U;
+ rmIrqRel.dst_id = TISCI_DEV_MCU_R5FSS0_CORE0;
+ rmIrqRel.secondary_host = TISCI_HOST_ID_MCU_0_R5_0;
+ rmIrqRel.dst_host_irq = INTRTR_CFG_MBX_CLST0_USR1_437_MPU_1_0_TO_MCU_1_0_376;

You can apply the patch on SDK 9.1.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1333580/faq-tda4vh-q1-cdd_ipc_app_rc_linux-example-for-j784s4-is-not-present-in-sdk-9-1

RegardS

Tarun Mukesh

Hi Tarun, a couple of questions, first one is about patch suggested, I tried to apply it on sdk-rtos-j784s4-evm-09_02_00_05 and its seems is not fully apply, not sure why but getting below error:

In some files it seems is applied properly but in other ones I am not sure the entire list of files affected by the patch, my main concern is that I am following files referenced on the patch wiki [FAQ] TDA4VH-Q1: CDD_IPC_APP_RC_LINUX example for J784S4 is not present in SDK 9.1 - Processors forum - Processors - TI E2E support forums for example, CddIpcAppStartup.c but only existing ones are for j721e and j7200 so not sure if that information is reliable for implementation purposes. 

Let me summarize my questions:

• Is that error after applying the patch expected, if not any suggestion to apply it properly?
• Is normal no folder inside cddIpcRProcLinux for j784s4?
• Based on example ISR can be configured on Cdd_IpcApp_MbIntRegForMpu10() inside CddIpcAppStartup.c but in addition to that, something needs to be configured on OS (.arxml)?

Hello,

As it is mentioned in the patch, it is for SDK 9.1 and you need to port the example into SDK 9.2 rather than directly applying the patch.

You could add the files as needed and do the changes proposed in the patch.

Regards

Tarun Mukesh