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AM3354: Watchdog or Watchdog0

Kevin Peng
Expert 3752 points
Part Number: AM3354

Tool/software:

Hi TI Experts,

Customer is working on SDK5.2.

They have a problem that will produce around running a month that will cause the system stuck, and no error log shown for analyze. We have tried our best turn on most of the debug configurations in the kernel config file, but still after half a year trying, we still do not get any information when the system stuck.

Hence, an alternative way I am thinking is to enable our internal watchdog, so that every time when the system stuck after a month, the watchdog will reset our system to keep running.

Customer also validated the watchdog function on their board by manually creating a system crash problem and make the system stuck, then after some time the watchdog will make the system reboot and run normally.

We now plan to use this solution to run a month and see if the original problem happens if we could successfully reboot the system using watchdog.

There are 3 things may need your help before we do that.

1: We see there are /dev/watchdog  and  /dev/watchdog0 in the coding, which one shall we use? We want to know whether watchdog or watchdog0 connects to our hardware module WDT shown below.

We want to make sure the watchdog we used actually is triggering our WDT hardware module to send the reset signal. Not like we type "reboot" command to reboot from software. So that when the problem comes we will have more chance to survive.

2: How do we know the reset is triggered from the watchdog, could you please provide a command to read the register so that we could know after watchdog reset?

3: Will the watchdog reset only do the warm reset or it will also trigger the PORZ?

Many Thanks,

Kevin

  • 0
    TI__Guru** 100560 points

    Hello Kevin,

    Limited support available 

    Heads up, Linux SDK 5.2 (kernel version 4.14 if I remember correctly?) is too old for us to support on the forums. I will provide general guidance about the hardware, but I will not be able to comment on anything specific to SDK 5.2 as opposed to our more recent versions of the Linux SDK.

    which /dev/watchdog to use?

    /dev/watchdog and /dev/watchdog0 are the same thing. As far as I am aware it makes no difference which one you use.

    On processors with multiple watchdog timers (e.g., AM64x), then you will see /dev/watchdog, /dev/watchdog0, /dev/watchdog1, etc. For those processors, I cannot remember if /dev/watchdog always equals /dev/watchdog0, or if it can change. But that does not impact you on AM335x.

    How do you know if reset has been triggered on watchdog? 

    Off the top of my head, I am not sure of the best way to do this.

    AM335x does have the WDT_WDST (Watchdog Status Register). From the AM335x Technical Reference Manual (TRM):

    But I have not played around with AM335x registers at this point. My assumption is that this register would stay at 0x0 if it attempted a reset of the processor and the processor did not actually reset, but I cannot say for sure.

    You can use the devmem2 tool to read register values from the Linux terminal.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Expert 3752 points

    Hi Nick,

    Thanks for your information!

    And for the watchdog register, I also found this one below, we could know the warm reset is coming from Watchdog or SW by reading this register 0x44E00F08.

    Thanks,

    Kevin

  • 0 in reply to Nick Saulnier
    TI__Expert 3752 points

    Hi Nick,

    May I know is the internal watchdog doing the warm reset or cold reset?

    For example, will there be power off / on happens when watchdog triggers?

    If this only does the warm reset, is there a way to do the cold reset?

    Thanks,

    Kevin

  • 0 in reply to Kevin Peng
    TI__Guru** 100560 points

    Hello Kevin,

    From the Linux driver side, I do not see any place to specify what kind of reset to put the chip into when the watchdog times out. I also do not see any settings hardcoded into the Linux kernel watchdog driver. I am sending your thread over to a member of our hardware team to comment.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru**** 188469 points

    Hello Kevin,

    Please refer below.

    8.1.7.3 Global Power On Reset (Cold Reset)

    8.1.7.5 Reset Characteristics The following table shows characteristic of each reset source.

    20.4.3.5 Overflow/Reset Generation

    When the watchdog timer counter register (WDT_WCRR) overflows, an active-low reset pulse is generated to the PRCM module. This RESET pulse causes the PRCM module to generate global WARM reset of the device, which causes the nRESETIN_OUT pin to be driven out of the device. This pulse is one prescaled timer clock cycle wide and occurs at the same time as the timer counter overflow.

    Looks like the warchdog can generate only global warm reset.

    I am also checking with the internal expert.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Mastermind 27260 points

    Hi,

    Closing the thread, as there is no response for long. Feel free to ping back, if you want to continue discussion.

    Regards

    Ashwani