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SK-AM62B-P1: Unable to write into GIC memory region (GICSS0_GIC)

YUFENG XIE
Prodigy 70 points
Part Number: SK-AM62B-P1


Tool/software:

Hi TI,

I am trying to enable the software interrupt on a53 multicores.

What I have done is write the interrupt No. (macro from GICSS0_COMMON_0) and the binding CPU core No. into GICSS0_GIC region(start from 0x01800000).

However, the debug process told me that the value in GIC region has not changed after the assignment operation.

I've also tried to change the value in GIC region manually in debug mode, but every time I performed [step into], the value in GIC region went back to 0.

How can I make the GIC region writable? 

Regards,

Xie

  • 0
    Prodigy 70 points
    The following code is the assignment operation.
    gic refers to the address of GICSS0_GIC region,and gic->dist->cpu_target[index] is where the CPU core No. should be stored but actually not changed.
    -------------------------------------------------------------------------------------------------------------
     *sorry for the editing, my team leader required me to delete the source code for confidential issues*
  • 0 in reply to YUFENG XIE
    TI__Genius 12980 points

    Hi,

    I have assigned your query to the concerned expert. Please wait for their response.

    Regards,
    Aparna

  • 0 in reply to Aparna Patra
    TI__Genius 14915 points

    Hi Xie,

    Could you provide more information on this:

    1. Please let me know which MCU + SDK version you are using for this.

    2. Please provide more details on your use case: From which module you are generating this interrupt? What is the interrupt number you are trying to generate? How are you planning to generate the trigger using software? Also, which core you are planning to route this interrupt to?

    3. Let me know which register you are referring to when you say gic->dist->cpu_target[index], is it GICD_ITARGETSRn or GICD_SGIR

    Best Regards,

    Meet.

  • 0 in reply to Meet Thakar
    Prodigy 70 points

    Hi Meet,

    We are developing some application on rtos.

    1. the dev is based on mcu_plus_sdk_am62x_09_01_00_39

    2. We are using Display SubSystem module to generate the interrupt.

    The interrupt number 116 is referred to the following header file.

    mcu_plus_sdk_am62x_09_01_00_39\source\drivers\hw_include\am62x\cslr_intr_gicss0_common_0.h

    We had some third-party software that fits our rtos to generate the trigger. 

    I am trying to sign the interrupt to cores other than CPU0.

    3. GICD_ITARGETSRn

    While the DSS doc for AM62x has not been released yet, we are referring to the following link AM62Px MCU+ SDK: DSS

    Best Regards,

    Xie

  • +1 in reply to YUFENG XIE
    TI__Genius 14915 points

    Hi Xie-San,

    For AM62x, All the A53 cores share the same GIC controller, so each interrupt is routed to all cores, please refer to section 10.1 Interrupt Architecture in AM62x TRM for more details. Because of this reason ITARGET registers are reserved and you can't write to it (refer to section 14.6.1 in TRM):

    Best Regards,

    Meet,

  • +1 in reply to Meet Thakar
    Prodigy 70 points

    Hi Meet,

    Thanks a lot for your answer!

    I still have some questions about the interrupt.

    I set a breakpoint inside the interrupt function in debug mode. Everytime the program stopped at the breakpoint, the interrupt handle function was always running on CPU0, which is the main core of a53.

    However, according to the explaination「All four A53 cores share the same GICSS」from TRM section 10.1, does it mean the interrupt function would occur in all four cores? I have not seen the interrupt handle function happen in other cores in debug mode yet.

    Best Regards,

    Xie

    *edit*  interrupt function ->interrupt handle function

  • 0 in reply to YUFENG XIE
    TI__Genius 14915 points

    Hi Xie-San,

    I am checking this with our team, will get back to you as soon as I have an update.

    Best Regards,

    Meet.

  • +1 in reply to Meet Thakar
    TI__Genius 14915 points

    Hi Xie-San,

    Currently in MCU + SDK all the peripheral interrupts and resources are allocated only to A530_0 core only, to work on A530_1 core we need to split interrupts to both cores and resources are partitioned in between both cores. This is not done in MCU+SDK. Please check the MCU + SDK release notes for this info.

    Best Regards,

    Meet.

  • 0 in reply to Meet Thakar
    Prodigy 70 points

    Hi Meet,

    Thank you for the investigation. It almost resolved my questions. 

    Best Regards,

    Xie