This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6670 fixed CVDD use instead of using SmartReflex

Other Parts Discussed in Thread: UCD9222

Can I use a fixed CVDD to the 6670?  My application isn’t concerned with reducing power and it seems that this is the primary reason for its implementation.

 

Referring to SPRABI2, section 5.9 it indicates that the KeyStone DSP supports SmartReflex Class 0 and Class 3.

Class 0 is defined in 5.9.3 indicates there is a single value determine at manufacturing time and programmed into each die.

It further says that “In this class of operation (Class 0) only the VCNTL or VID interface

connections are used to program a fixed value of the external power source.”

If I am about to use a fixed voltage for CVDD, why would I need this connection and to what exactly?

 

Referring to SPRUGV4A, 3.2.2 where the VCNTLID register is defined, 6 bits from 21 to 16 which are all read only seem to be the value I am looking for Class 0 operation. If I had those bits, is it a simple matter of looking up the required voltage level in Table 10 section 5.9 of SPRABI2 and setting my CVDD to that?

 

If all of this is correct, what voltage should be used for CVDD initially to establish a communication pathway with the device so that the VCNTLID bits can be retrieved to adjust my CVDD regulator?

  • You cannot use a fixed voltage for the CVDD.  The C6670 will request the voltage it needs using the VCNTL bus as part of the reset cycle.  Initially the CVDD should be set to 1.05V and then changed to the value presented on the VCNTL lines.  Note that the CVDD voltage requested by the processor could be different for each DSP in your design and separate CVDD supplies are needed for each.  Presently design examples using the UCD9222 power supply controller are available and supported by TI.  The UCD9222 can be programmed to interface directly with the VCNTL interface and interpret the six bit value presented as the proper voltage level required. 

  • Would like to ask why we cannot use a fixed voltage for the CVDD. From datasheet and product brief, it says that the SmartReflex is used to optimize power and performance. Hence if we do not need to optimize these 2 (power and performance) and we need to optimize PCB space, then we could use a smaller regulator for CVDD?

    Are you saying that the CVDD voltage will be different for different application. Say for a low intensive processing C66, the voltage will be lower vs for a highly intensive processing C66.

    Another question is will the CVDD voltage requirement change with time. For example, at the start the voltage may be 1.05V. Later, it stabilize to 1V. Later in intensive processing, it will jump to 1.1V?

    If we supply a fixed 1V to C66, what will happen when the c66 requires 1.05V? Will the C66 stop working. I thought normally there is a tolerance. So we just need to provide the required tolerance will be sufficient. A 1V fixed regulator should be okay for C66 with CVDD which ranges from 0.9 to 1.1V and is of 10% tolerance.