Can I use a fixed CVDD to the 6670? My application isn’t concerned with reducing power and it seems that this is the primary reason for its implementation.
Referring to SPRABI2, section 5.9 it indicates that the KeyStone DSP supports SmartReflex Class 0 and Class 3.
Class 0 is defined in 5.9.3 indicates there is a single value determine at manufacturing time and programmed into each die.
It further says that “In this class of operation (Class 0) only the VCNTL or VID interface
connections are used to program a fixed value of the external power source.”
If I am about to use a fixed voltage for CVDD, why would I need this connection and to what exactly?
Referring to SPRUGV4A, 3.2.2 where the VCNTLID register is defined, 6 bits from 21 to 16 which are all read only seem to be the value I am looking for Class 0 operation. If I had those bits, is it a simple matter of looking up the required voltage level in Table 10 section 5.9 of SPRABI2 and setting my CVDD to that?
If all of this is correct, what voltage should be used for CVDD initially to establish a communication pathway with the device so that the VCNTLID bits can be retrieved to adjust my CVDD regulator?