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DRA829V: UART FIFO Polling mode

Part Number: DRA829V
Other Parts Discussed in Thread: DRA829

Tool/software:

Hello,

I am working on UART module. I want to use UART Module in FIFO Polling Mode with FIFO enabled for 64 bytes. I am refering to the Chapter 12.1.6.4.6.3 FIFO Polled Mode Operation in the Technical Reference Manual.

It says that "In FIFO polled mode (the [0] FIFO_EN bit is set to 0 and the relevant interrupts are disabled by the register), the status of the receiver and transmitter can be checked by polling the line status register ()".

Does it means that to use 64 byte FIFO in polling mode, the UART_FCR register - FIFO_EN field need to be set to 0 ? 

Best Regards,

Vivek

  • Hi Vivek,

    Does it means that to use 64 byte FIFO in polling mode, the UART_FCR register - FIFO_EN field need to be set to 0 ? 

    For using the 64 byte FIFO polling mode,the UART_FCR register must be set to 1 according to the DRA829 TRM

  • Hi Gokul,

    Thanks for the reply. Then I am using it in the correct way. The description written in DRA829 TRM Chapter 12.1.6.4.6.3 FIFO Polled Mode Operation for FIFO_EN is incorrect.

    I have one more question regarding the RX_FIFO_TRIG and TX_FIFO_TRIG in UART_FCR register. As per my understanding to use UART in FIFO polling mode I do not need to set these fields because they are used for FIFO interrupt mode. 

    Did I understand it correctly ?

  • The description written in DRA829 TRM Chapter 12.1.6.4.6.3 FIFO Polled Mode Operation for FIFO_EN is incorrect.

    Oh,really sorry for that vivek.We will correct it.

    I have one more question regarding the RX_FIFO_TRIG and TX_FIFO_TRIG in UART_FCR register. As per my understanding to use UART in FIFO polling mode I do not need to set these fields because they are used for FIFO interrupt mode. 

    Yes,you understood it correctly,Vivek.