TDA4AL-Q1: Tda4AL cpsw2g / cpsw2g-main crash with heavy network traffic

Eric Tsai

Part Number: TDA4AL-Q1

Tool/software:

Hi expert,

we have the same issue as below URL described :
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1113291/tda4vm-tda4vm-qnx-2g-9g

OS : QNX 7.1 with sdk 8.0.6

I dont see any solution has been provide on the URL reply

Could you please double check internally if the issue has been solve, and where can we get the patch

Thanks

20 days ago

0 Praveen Rao 20 days ago

TI__Mastermind 35872 points

Hello Eric,

How are these drivers started, and what is the use case that mandates running both CPSW2G and CPSW9G together? Also, 8.0.6 is very old, so have you tried any newer SDK?

Thanks.

0 Eric Tsai 20 days ago in reply to Praveen Rao

Prodigy 195 points

Hi Praveen,

We are start those drivers by io-pkt-v4-hc

Then mount cpsw2g.so and cpsw2g-main.so as io-pkt

We are use cpsw2g and cpsw2g-main

We also have try 9.2.0 SDK and got the same symptom

0 Praveen Rao 20 days ago in reply to Eric Tsai

TI__Mastermind 35872 points

Hi Eric,

Please share the complete log (including the slog) and the symptoms. Also, share the full "devnp" directory source for us to look at and provide the patch for you to try. Alternatively, suggest testing our latest 10.0 release (replace the "devnp" dir content).

Thanks.

0 Eric Tsai 19 days ago in reply to Praveen Rao

Prodigy 195 points

Hi Praveen,

please find the log as attachment

TDA4_error.txt

[BEGIN] 2024/11/13 17:42:02
TDCU4@QNX:/# 
U-Boot SPL 2021.01 (Jul 12 2024 - 15:16:01 +0800)
Model: TDCU4 R5 UB.R6.001 BW 4G
ti_sci system-controller@44083000: Message not acknowledgedti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara')
SPL initial stack usage: 13472 bytes
BOARD_ID: 10
Trying to boot from MMC1
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
init_env from device 17 not supported!
Starting ATF on ARM64 core...
U-Boot SPL 2021.01 (Jul 12 2024 - 15:15:52 +0800)
Model: TDCU4 UB.R6.001 4G
ti_sci system-controller@44083000: Message not acknowledgedti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara')
BOARD_ID: 10
Trying to boot from MMC1
U-Boot 2021.01 (Jul 12 2024 - 15:15:52 +0800)
SoC:   J721S2 SR1.0 GP
Model: TDCU4 UB.R6.001 4G
Board: TDCU4
U-Boot version: UB.006
BOARD_ID: 10
DRAM:  4 GiB
Flash: 0 Bytes
MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from MMC... OK
In:    serial@2890000
Out:   serial@2890000
Err:   serial@2890000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
FRU Version: 2
FRU Header: ee3355aa
BI Header: eeaa5511
PI Header: 57f3f586
Manufacturer: Foxconn Industrial Internet
Board PROD DT: 2024/09/23
Board Name: TDCU4
Board Version: X07
Board PN: 1A7277700-600-G
Board SN: 1A7277700X0749R00B
GPIO0_27: 0
GPIO0_30: 1
ENV boot_partition=A
Net:   Could not get PHY for ethernet@46000000port@1: addr 10
am65_cpsw_nuss_port ethernet@46000000port@1: phy_connect() failed
No ethernet found.
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc0(part 0) is current device
SD/MMC found on device 0
Failed to load 'boot.scr'
Failed to load 'uEnv.txt'
10 bytes read in 5 ms (2 KiB/s)
Base Address: 0x82000000
10 bytes written in 5 ms (2 KiB/s)
Checked Boot File System
Running uenvcmd ...
k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work
k3_r5f_rproc r5f@41400000: Core 2 is already in use. No rproc commands work
1010792 bytes read in 20 ms (48.2 MiB/s)
Load Remote Processor 2 with data@addr=0x82000000 1010792 bytes: Success!
297868 bytes read in 31 ms (9.2 MiB/s)
Load Remote Processor 3 with data@addr=0x82000000 297868 bytes: Success!
Failed to load '/lib/firmware/j721s2-main-r5f1_0-fw'
Failed to load '/lib/firmware/j721s2-main-r5f1_1-fw'
14815240 bytes read in 71 ms (199 MiB/s)
Load Remote Processor 6 with data@addr=0x82000000 14815240 bytes: Success!
9760640 bytes read in 74 ms (125.8 MiB/s)
Load Remote Processor 7 with data@addr=0x82000000 9760640 bytes: Success!
11621256 bytes read in 89 ms (124.5 MiB/s)
## Starting application at 0x80080000 ...
BOARD_ID: 10
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
ARM GIC-500 r1p1, arch v3.0 detected
gic_v3_lpi_add_entry for vectors 8192 -> 8447, Ok
gic_v3_lpi_add_entry for vectors 8448 -> 65535, Ok
No SPI intrinfo. Add default entry for 32 -> 991 vectors, Ok
LPI config table #1 @ 000000008000f000, callout vaddr: ffffff8040251000
aarch64_cpuspeed: core speed 2000
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Enabling ITS 0
ITS queue at 0000000080020000, num slots: 256
Issue MAPC/SYNC/INVALL commands for ICID 0
update CWRITER to 0x00000060
Waiting for all commands to be processed ... Done in 1 tries
Enable LPIs in GICR_CTLR @ 0000000001900000 for CPU0
Display set to A72
Total Available L3 cache (MSMC SRAM): 4194304 bytes
Loading IFS...decompressing...done
aarch64_cpuspeed: core speed 2000
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16
ITS 0 already Enabled
ITS queue at 0000000080020000, num slots: 256
Issue MAPC/SYNC/INVALL commands for ICID 1
update CWRITER to 0x000000c0
Waiting for all commands to be processed ... Done in 1 tries
Enable LPIs in GICR_CTLR @ 0000000001920000 for CPU1
System page at phys:0000000080023000 user:ffffff8040275000 kern:ffffff8040272000
Starting next program at vffffff8060087300
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.1.0 on the TDCU4-CD Board!!
Starting random service ...
start serial driver
start i2c driver
Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Setting environment variables...
done..
Mounting the emmc ..
Path=0 - am65x
 target=0 lun=0     Direct-Access(0) - SDMMC: DG4008 Rev: 0.1
Booting to qnxfs_a
mount /dev/emmc0.ms.4
Mounting OTA and Userdata directory ...
Looking for user script to run: /ti_fs/scripts/user.sh
Running user script...
user.sh called...
Setting additional environment variables...
Version: QNX.R5.008
Starting tisci-mgr..
Starting shmemallocator..
Starting tiipc-mgr..
Mounting OTA and Userdata directory Done
Starting tiudma-mgr..
force change GTC CLK to 200M
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | QNX (version v1.0.5-137-gc1339e23d built Tue Nov 5 01:10:35 UTC 2024) |
| SoC    | J721S2 SR1.0                                                          |
| SYSFW  | ABI: 3.1 (firmware version 0x0008 '8.6.3--1-g2249f (Chill Capybara)') |
|--------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                        | Status          | Clock Frequency |
|------------------------------------------------------------------------------------------------------------------------------|
|    61     |     0    | DEV_GTC0_VBUSP_CLK                                                | CLK_STATE_READY | 125000000       |
|    61     |     1    | DEV_GTC0_GTC_CLK                                                  | CLK_STATE_READY | 200000000       |
|    61     |     2    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | CLK_STATE_READY | 250000000       |
|    61     |     3    | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | CLK_STATE_READY | 200000000       |
|    61     |     4    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | CLK_STATE_READY | 0               |
|    61     |     5    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | CLK_STATE_READY | 0               |
|    61     |     6    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | CLK_STATE_READY | 0               |
|    61     |     7    | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | CLK_STATE_READY | 0               |
|    61     |     8    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK        | CLK_STATE_READY | 0               |
|    61     |     9    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK        | CLK_STATE_READY | 0               |
|    61     |    10    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK        | CLK_STATE_READY | 0               |
|    61     |    11    | DEV_GTC0_GTC_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK        | CLK_STATE_READY | 0               |
|    61     |    16    | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | CLK_STATE_READY | 500000000       |
|    61     |    17    | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000       |
|------------------------------------------------------------------------------------------------------------------------------|
force change CPSW_CPTS_RFT_CLK to 500M
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | QNX (version v1.0.5-137-gc1339e23d built Tue Nov 5 01:10:35 UTC 2024) |
| SoC    | J721S2 SR1.0                                                          |
| SYSFW  | ABI: 3.1 (firmware version 0x0008 '8.6.3--1-g2249f (Chill Capybara)') |
|--------------------------------------------------------------------------------|
|------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                              | Status          | Clock Frequency |
|------------------------------------------------------------------------------------------------------------------------------------|
|    28     |     0    | DEV_CPSW1_MDIO_MDCLK_O                                                  | CLK_STATE_READY | 0               |
|    28     |     1    | DEV_CPSW1_CPTS_GENF0                                                    | CLK_STATE_READY | 0               |
|    28     |     3    | DEV_CPSW1_CPTS_RFT_CLK                                                  | CLK_STATE_READY | 500000000       |
|    28     |     4    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK         | CLK_STATE_READY | 500000000       |
|    28     |     5    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK       | CLK_STATE_READY | 200000000       |
|    28     |     6    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT             | CLK_STATE_READY | 0               |
|    28     |     7    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                 | CLK_STATE_READY | 0               |
|    28     |     8    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT               | CLK_STATE_READY | 0               |
|    28     |     9    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                   | CLK_STATE_READY | 0               |
|    28     |    10    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN0_TXMCLK        | CLK_STATE_READY | 0               |
|    28     |    11    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN1_TXMCLK        | CLK_STATE_READY | 0               |
|    28     |    12    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN2_TXMCLK        | CLK_STATE_READY | 0               |
|    28     |    13    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_WIZ16B8M4CT2_MAIN_0_IP2_LN3_TXMCLK        | CLK_STATE_READY | 0               |
|    28     |    18    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK          | CLK_STATE_READY | 500000000       |
|    28     |    19    | DEV_CPSW1_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000       |
|    28     |    20    | DEV_CPSW1_GMII1_MR_CLK                                                  | CLK_STATE_READY | 25000000        |
|    28     |    21    | DEV_CPSW1_GMII_RFT_CLK                                                  | CLK_STATE_READY | 125000000       |
|    28     |    22    | DEV_CPSW1_RGMII1_RXC_I                                                  | CLK_STATE_READY | 0               |
|    28     |    26    | DEV_CPSW1_RMII_MHZ_50_CLK                                               | CLK_STATE_READY | 0               |
|    28     |    27    | DEV_CPSW1_RGMII1_TXC_O                                                  | CLK_STATE_READY | 0               |
|    28     |    28    | DEV_CPSW1_CPPI_CLK_CLK                                                  | CLK_STATE_READY | 320000000       |
|    28     |    29    | DEV_CPSW1_RGMII_MHZ_5_CLK                                               | CLK_STATE_READY | 5000000         |
|    28     |    30    | DEV_CPSW1_GMII1_MT_CLK                                                  | CLK_STATE_READY | 25000000        |
|    28     |    32    | DEV_CPSW1_RGMII_MHZ_50_CLK                                              | CLK_STATE_READY | 50000000        |
|    28     |    33    | DEV_CPSW1_RGMII_MHZ_250_CLK                                             | CLK_STATE_READY | 250000000       |
|------------------------------------------------------------------------------------------------------------------------------------|
make ota_agent default folder
mkdir: /ota/agent: File exists
Starting Network driver...
Starting sshd
Configuring IP Address...
OTA is not running, wake up ota agent
/ti_fs/etc/ota_agent.sh[12]: /ti_fs/usr/bin/ota_agent: cannot execute - No such file or directory
Looking for camera script to run: /ti_fs/vision_apps/boot_auto_run_camera_360.sh
done...
TDCU4@QNX:/# 
Process 180239 (io-pkt-v4-hc) terminated SIGBUS code=3 fltno=6 ip=00000051608af7fc(/proc/boot/libc.so.5@pthread_mutex_unlock+0x0000000000000044) mapaddr=00000000000367fc.


[END] 2024/11/13 17:44:08

console log , you can see the crash is happens on pthread_mutex_unlock

//e2e.ti.com:443/cfs-filesystemfile/__key/communityserver-discussions-components-files/791/TDA4_5F00_io_5F00_pkt_5F00_v4_5F00_hc.180240.txt?_=638671695400088380" class="code-download ui-tip" data-tip="Download TDA4_io_pkt_v4_hc.180240.txt">TDA4_io_pkt_v4_hc.180240.txt data-mode="text" data-theme="light" style="height:240px;min-width:320px;margin:0px;" data-gutter="true">[BEGIN] 2024/11/13 17:37:39 slog2info -l /var/log/slogger2/io_pkt_v4_hc.180240 num_buffers=1 io_pkt_v4_hc.180240 slog* 0 cpsw_entry:546 Entry --> io_pkt_v4_hc.180240 slog 0 cpsw_attach:718 Entry --> io_pkt_v4_hc.180240 slog 0 cpsw_parse_options:222 mac_to_mac -->1 io_pkt_v4_hc.180240 slog 0 cpsw_parse_options:235 speed -->100 io_pkt_v4_hc.180240 slog 0 cpsw_parse_options:210 PTP -->1 io_pkt_v4_hc.180240 slog 0 Enable RGMII delay, regData = 0x12 io_pkt_v4_hc.180240 slog 0 Success - write to MAIN_ENET_CTRL - 0x12 io_pkt_v4_hc.180240 slog 0 Success - write to MAIN CPSW_CLKSEL - 0x0 io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930c0=0x50006 (org=0x50007) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930bc=0x50006 (org=0x50007) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930b8=0x50006 (org=0x50006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930a0=0x50006 (org=0x50006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930a4=0x50006 (org=0x50006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930a8=0x50006 (org=0x50006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930b0=0x50006 (org=0x50006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930ac=0x50006 (org=0x50006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x9029308c=0x50006 (org=0x10006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x90293090=0x50006 (org=0x10006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x90293094=0x50006 (org=0x10006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x90293098=0x50006 (org=0x10006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x902930b4=0x50006 (org=0x10006) io_pkt_v4_hc.180240 slog 0 Pinmux for 0x9029309c=0x50006 (org=0x10006) io_pkt_v4_hc.180240 slog 0 cpsw_entry:546 Entry --> io_pkt_v4_hc.180240 slog 0 cpsw_attach:718 Entry --> io_pkt_v4_hc.180240 slog 0 cpsw_parse_options:235 speed -->100 io_pkt_v4_hc.180240 slog 0 Success - write to MCU_ENET_CTRL - 0x12 io_pkt_v4_hc.180240 slog 0 Success - write to MCU_ENET_CLKSEL - 0xf00 io_pkt_v4_hc.180240 slog 0 Enabling clocks! io_pkt_v4_hc.180240 slog 0 EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:3 From 1 To 0 io_pkt_v4_hc.180240 slog 0 ENET_CPSW_2G on MAIN NAVSS io_pkt_v4_hc.180240 slog 56 [UDMA] Calling Udma_resmgr_open io_pkt_v4_hc.180240 slog 56 [UDMA] Opening resmgr!!! io_pkt_v4_hc.180240 slog 56 [UDMA] Opened resmgr fd=6!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->vintrNum = 35!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->irIntrNum = 11!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->coreIntrNum = 75!!! io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr2: tx isr 75 thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/75 coid/1073741849 event/c io_pkt_v4_hc.180240 slog 0 Enet_open: main.cpsw2g: features: 0x00000002 io_pkt_v4_hc.180240 slog 0 Enet_open: main.cpsw2g: errata : 0x00000000 io_pkt_v4_hc.180240 slog 0 Mdio_open: MDIO manual mode enabled io_pkt_v4_hc.180240 slog 0 cpsw_alloc:299: Alloc successfull; Virt: 0x329925a000, Phys: 0x8fc180000 io_pkt_v4_hc.180240 slog 0 EnetUdma_memMgrInit: addr=0x329925a000 is aligned io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr: some unknown cpsw isr thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/51 coid/1073741853 event/d io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr: some unknown cpsw isr thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/53 coid/1073741855 event/e io_pkt_v4_hc.180240 slog 0 cpsw_alloc:299: Alloc successfull; Virt: 0x32992f6000, Phys: 0x8fc194000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: addr=0x32992f6000 is aligned io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: addr=0x32992f6000, size=0x221000, gMem=0x32992f6000, gMemBufPhys=0x8fc194000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: gDmaDescMemArray=0x32992f6000, size=0x200000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: gRingMemArray=0x32994f6000, size=0x21000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: gDmaDescMemArrayBasePhys=0x8fc194000, gDmaDescMemArrayBase=0x32992f6000 io_pkt_v4_hc.180240 slog 0 initQs() freePktInfoQ initialized with 256 pkts io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->globalEvent = 34!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->vintrNum = 36!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->vintrBitNum = 0!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->irIntrNum = 12!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->coreIntrNum = 76!!! io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr2: rx isr 76 thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/76 coid/1073741856 event/f io_pkt_v4_hc.180240 slog 0 Host MAC address: io_pkt_v4_hc.180240 slog 0 70:ff:76:1d:92:c1 io_pkt_v4_hc.180240 slog 0 EnetIf_Init: 834 Info EnetIf_Init AleBcastEntry status = 0 io_pkt_v4_hc.180240 slog 0 EnetIf_PtpInit:562 PTP io_pkt_v4_hc.180240 slog 0 EnetIf_PtpInit:582 CPSW_CPTS_IOCTL_REGISTER_STACK is sucessful io_pkt_v4_hc.180240 slog 0 cpsw_init:1070 Phy is linked io_pkt_v4_hc.180240 slog 0 cpsw_filter: Clear IFF_ALLMULTI io_pkt_v4_hc.180240 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01 io_pkt_v4_hc.180240 slog 0 EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0 io_pkt_v4_hc.180240 slog 0 EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 1 To 0 io_pkt_v4_hc.180240 slog 0 ENET_CPSW_2G on MCU NAVSS io_pkt_v4_hc.180240 slog 56 [UDMA] Calling Udma_resmgr_open io_pkt_v4_hc.180240 slog 56 [UDMA] Opening resmgr!!! io_pkt_v4_hc.180240 slog 56 [UDMA] Opened resmgr fd=8!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->vintrNum = 37!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->irIntrNum = 13!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->coreIntrNum = 77!!! io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr2: tx isr 77 thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/77 coid/1073741858 event/10 io_pkt_v4_hc.180240 slog 0 Enet_open: cpsw2g: features: 0x00000002 io_pkt_v4_hc.180240 slog 0 Enet_open: cpsw2g: errata : 0x00000000 io_pkt_v4_hc.180240 slog 0 Mdio_open: MDIO manual mode enabled io_pkt_v4_hc.180240 slog 0 cpsw_alloc:299: Alloc successfull; Virt: 0x32a259a000, Phys: 0x8fc476000 io_pkt_v4_hc.180240 slog 0 EnetUdma_memMgrInit: addr=0x32a259a000 is aligned io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr: cpsw stat isr thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/888 coid/1073741862 event/11 io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr: cpsw cpts isr thread priority set to 22 io_pkt_v4_hc.180240 slog 0 EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/890 coid/1073741864 event/12 io_pkt_v4_hc.180240 slog 0 SetPhyConfig: got phy address = 10 io_pkt_v4_hc.180240 slog 0 EnetPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks) io_pkt_v4_hc.180240 slog 0 EnetPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks) io_pkt_v4_hc.180240 slog 0 EnetPhy_bindDriver: PHY 10: OUI:080028 Model:27 Ver:01 <-> 'dp83tc812' io_pkt_v4_hc.180240 slog 0 Dp83tc812_isPhyDevSupported : PHY OUI = 0x80028 io_pkt_v4_hc.180240 slog 0 Dp83tc812_isPhyDevSupported : PHY MODEL = 0x0027 io_pkt_v4_hc.180240 slog 0 Dp83tc812_isPhyDevSupported : PHY REVISION = 0x0001 io_pkt_v4_hc.180240 slog 0 Dp83tc812_isMacModeSupported: mii = 0x0003 io_pkt_v4_hc.180240 slog 0 EnetPhy_bindDriver: PHY 10: OUI:080028 Model:27 Ver:01 <-> 'dp83tc812' : OK io_pkt_v4_hc.180240 slog 0 EnetPhy_open: PHY 10: open io_pkt_v4_hc.180240 slog 0 cpsw_alloc:299: Alloc successfull; Virt: 0x32a2656000, Phys: 0x8fc4ca000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: addr=0x32a2656000 is aligned io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: addr=0x32a2656000, size=0x221000, gMem=0x32a2656000, gMemBufPhys=0x8fc4ca000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: gDmaDescMemArray=0x32a2656000, size=0x200000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: gRingMemArray=0x32a2856000, size=0x21000 io_pkt_v4_hc.180240 slog 0 EnetIfMem_init: gDmaDescMemArrayBasePhys=0x8fc4ca000, gDmaDescMemArrayBase=0x32a2656000 io_pkt_v4_hc.180240 slog 0 initQs() freePktInfoQ initialized with 256 pkts io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->globalEvent = 35!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->vintrNum = 38!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->vintrBitNum = 1!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->irIntrNum = 14!!! io_pkt_v4_hc.180240 slog 56 [UDMA] eventHandle->coreIntrNum = 78!!! io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr2: rx isr 78 thread priority set to 21 io_pkt_v4_hc.180240 slog 0 EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/78 coid/1073741865 event/13 io_pkt_v4_hc.180240 slog 0 Host MAC address: io_pkt_v4_hc.180240 slog 0 28:b5:e8:cc:1c:9f io_pkt_v4_hc.180240 slog 0 EnetIf_Init: 834 Info EnetIf_Init AleBcastEntry status = 0 io_pkt_v4_hc.180240 slog 0 PHY 10 is alive io_pkt_v4_hc.180240 slog 0 Dp83tc812_reset: PHY 10: global soft-reset io_pkt_v4_hc.180240 slog 0 IsMaster is 0x0 io_pkt_v4_hc.180240 slog 0 EnetPhy_setNextState: PHY 10: FOUND -> RESET_WAIT (10 ticks) io_pkt_v4_hc.180240 slog 0 Dp83tc812_isResetComplete: PHY 10: global soft-reset is complete io_pkt_v4_hc.180240 slog 0 EnetPhy_setNextState: PHY 10: RESET_WAIT -> ENABLE (0 ticks) io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: enable io_pkt_v4_hc.180240 slog 0 Dp83tc812_restart: PHY 10: soft-restart io_pkt_v4_hc.180240 slog 0 Dp83tc812_setMiiMode: PHY 10: MII mode: 3 io_pkt_v4_hc.180240 slog 0 Dp83tc812_setClkDelay: PHY 10: set delay 0 ps TX, 0 ps RX io_pkt_v4_hc.180240 slog 0 Dp83tc812_setTxFifoDepth: PHY 10: set FIFO depth 5 io_pkt_v4_hc.180240 slog 0 Dp83tc812_setLedMode: PHY 10: set LED0 = mode0, LED1 = mode0, LED2 = mode1, LED3 = mode0 io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: req caps: FD100 io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: PHY caps: FD100 HD100 io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: MAC caps: FD1000 FD100 HD100 FD10 HD10 io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: refined caps: FD100 io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: PHY is not NWAY-capable io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: falling back to manual mode io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: new link caps: FD100 io_pkt_v4_hc.180240 slog 0 EnetPhy_enableState: PHY 10: manual setup io_pkt_v4_hc.180240 slog 0 EnetPhy_setupManual: PHY 10: requested mode: 100 Mbps full-duplex io_pkt_v4_hc.180240 slog 0 EnetPhy_setNextState: PHY 10: ENABLE -> LINK_WAIT (50 ticks) io_pkt_v4_hc.180240 slog 0 EnetPhy_setNextState: PHY 10: LINK_WAIT -> LINKED (0 ticks) io_pkt_v4_hc.180240 slog 0 Cpsw_isPortLinkUp: Port 1: Sublayer 1 doesn't support link status io_pkt_v4_hc.180240 slog 0 Cpsw_handleLinkUp: Port 1: Link up: 100-Mbps Full-Duplex io_pkt_v4_hc.180240 slog 0 cpsw_init:1070 Phy is linked io_pkt_v4_hc.180240 slog 0 cpsw_filter: Clear IFF_ALLMULTI io_pkt_v4_hc.180240 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01 io_pkt_v4_hc.180240 slog 0 cpsw_filter: Clear IFF_ALLMULTI io_pkt_v4_hc.180240 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 01:80:c2:00:00:0e io_pkt_v4_hc.180240 slog 0 cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01 io_pkt_v4_hc.180240 slog 0 EnetIf_GetRx:2488 Error: failed to send packet.. ret--1

system log, nothing special.

io-pkt-v4-hc.core.zip

and core dump file, i've try to looking root cause by gdb, but nothing found.

about source code, i believe it can duplicate the issue on J721S2 QNX 9.2 SDK.

if you bring cpsw2g.so and cpsw2g-main.so together via below procedures

==================================

io-pkt-v4-hc

mount -T io-pkt -o speed=100,ptp=1 devnp-cpsw2g-main.so
if_up -p an0

mount -T io-pkt -o speed=100 devnp-cpsw2g.so
if_up -p am0

==================================

then follow below steps:

1. set a local ip for an0 and am0 (ex: 192.168.1.5 and 192.168.1.9)

2. start iperf3 server on TDA4. (iperf3 -s)

3. find two PC to connect to cpsw2g and cpsw2g-main Eth port

4. use iperf3 to run throughput test at same time

(iperf3 -c 192.168.1.5 -t 3600 / iperf3 -c 192.168.1.9 -t 3600)

then waiting for a while, the io-pkt-v4-hc will crashed like attachment described.

normally it's happen in 200seconds, but sometime it's possible to crash on 2500seconds +-

0 Praveen Rao 19 days ago in reply to Eric Tsai

TI__Mastermind 35872 points

Hi Eric,

We will review the code and get back to you as soon as we have completed the analysis. We will also share any relevant patches needed.

Thanks.

0 Praveen Rao 19 days ago in reply to Praveen Rao

TI__Mastermind 35872 points

Hi Eric,

We did not realize you had not shared the code for the "devnp" dir. Can you please provide that?

Thanks.

0 Praveen Rao 19 days ago in reply to Praveen Rao

TI__Mastermind 35872 points

Eric Tsai said:
about source code, i believe it can duplicate the issue on J721S2 QNX 9.2 SDK.

Other customers reported this on 9.2 and older releases, and we have asked them to take our 10.0 release "devnp" code. We suggest you do the same and test.

Thanks.

0 Eric Tsai 19 days ago in reply to Praveen Rao

Prodigy 195 points

Hi Praveen,

i am working on to porting 10.0 SDK to our platform right now.
Any result will feedback to you

BTW, it’s known issue on 9.2 and solved in 10.0 ?

0 Praveen Rao 18 days ago in reply to Eric Tsai

TI__Mastermind 35872 points

Hi Eric,

Yes, it is a known issue on 9.2 and earlier releases.

Thanks.

0 Namic Chang 18 days ago in reply to Praveen Rao

Prodigy 240 points

Hi Praveen:

I ported the "devnp" folder of SDK 10.00 and the crash still occurred.

The crash screen:

The slog:

eth_err_slog.txt

Jan 01 00:00:00.021                       random.5                  low*     0  qcrypto: loading configuration file '/etc/qcrypto.conf' [qcrypto_common.c(190)]
Jan 01 00:00:00.021                    random.5..0                 slog*   700  Random is using the Fortuna PRNG
Jan 01 00:00:00.027                       random.5                  low      0  qcrypto: 'openssl' plugin loaded [qcrypto_plugins.c(354)]
Jan 01 00:00:00.027                    random.5..0                 slog    700  Selecting timer as an entropy source
Jan 01 00:00:00.028                    random.5..0                 slog    700  Registered path names
Jan 01 00:00:00.028                    random.5..0                 slog    700  random: starting resmgr
Jan 01 00:00:00.028                    random.5..0                 slog    700  random: Daemonizing the process
Jan 01 00:00:00.049            devb_sdmmc_am65x.10                 slog*  1800  devb-sdmmc-am65x 1.00A (Nov 15 2024 12:25:12)
Jan 01 00:00:00.050            devb_sdmmc_am65x.10                 slog      0  libcam.so (Sep  3 2021 11:57:38) bver 7010004
Jan 01 00:00:00.051            devb_sdmmc_am65x.10                 slog   1800  sdio_cd:  insertion path 0, cd state 0x1
Jan 01 00:00:00.053            devb_sdmmc_am65x.11                 slog*  1800  devb-sdmmc-am65x 1.00A (Nov 15 2024 12:25:12)
Jan 01 00:00:00.053            devb_sdmmc_am65x.11                 slog      0  libcam.so (Sep  3 2021 11:57:38) bver 7010004
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800  MMC CID:
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    MID 0x45, OID 0x0, PNM DG4008
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    PRV 0x1, PSN 0x359de62f, MDT 2-2024
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800  MMC CSD:
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    CSD_STRUCTURE 3, SPEC_VERS 4, CCC 0x8f5
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    TAAC 15, NSAC 0, TRAN_SPEED 50
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    C_SIZE 4095, C_SIZE_MULT 7
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    READ_BL_LEN 9, WRITE_BL_LEN 9
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    ERASE GRP_SIZE 31, GRP_MULT 31, SIZE 0
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    blksz 512, sectors 2097152, dtr 25000000
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800  MMC EXT CSD:
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    DEVICE_TYPE 0x57, EXT_CSD_REV 8
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    SEC_COUNT 15273600, dtr 200000000
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    HC_ERASE_GRP_SIZE 1, HC_WP_GRP_SIZE 16
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    STROBE 0x1, BKOPS_EN 0x2
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800    Driver type: 0x0
Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog   1800  CFG:  Timing HS200, DTR 200000000, Bus Width 8 bit

Jan 01 00:00:00.137            devb_sdmmc_am65x.10                 slog    100  cam-disk.so (Sep  3 2021 11:57:42)
Jan 01 00:00:00.341               tisci_mgr.110606                 slog*   130  TI SCI ResMgr for SOC J721S2 (version=PSDKQNX_08_06_00, date=Fri Nov 15 12:24:27 CST 2024)
Jan 01 00:00:00.342               tisci_mgr.110606                 slog    130   SYSFW Firmware Version 8.6.3--1-g2249f (Chill Capybara
Jan 01 00:00:00.342               tisci_mgr.110606                 slog    130   SYSFW Firmware revision 0x8
Jan 01 00:00:00.342               tisci_mgr.110606                 slog    130   SYSFW ABI revision 3.1
Jan 01 00:00:00.375          shmemallocator.135184                 slog*   129  TI Shared memory Allocator for SOC J721S2 (version=PSDKQNX_08_06_00, date=Fri Nov 15 12:24:27 CST 2024)
Jan 01 00:00:00.375          shmemallocator.135184                 slog    129  initSHM:Block[0] @ 0xb8000000 has free-mem = 0x20000000 - 512 M
Jan 01 00:00:00.375          shmemallocator.135184                 slog    129  initSHM:Block[1] @ 0xe6000000 has free-mem = 0x2000000 - 32 M
Jan 01 00:00:00.416               tiipc_mgr.139281                 slog*   133  TI IPC ResMgr for SOC J721S2 (version=PSDKQNX_08_06_00, date=Fri Nov 15 12:24:27 CST 2024)
Jan 01 00:00:00.416               tiipc_mgr.139281                 slog    133  tiipc-mgr: Starting TI IPC Resmgr
Jan 01 00:00:00.416               tiipc_mgr.139281                 slog    133  tiipc-mgr: Using VRING base address: 0xa8000000, size:0x1c00000
Jan 01 00:00:00.450               tiipc_mgr.139281                 slog    133  [IPC] 
Jan 01 00:00:00.450               tiipc_mgr.139281                 slog    133  Mailbox_plugInterrupt: interrupt Number 489, arg 0xEBA6C0C8

Jan 01 00:00:00.450               tiipc_mgr.139281                 slog      0  Thread Priority set < 10, the value is 1!
Jan 01 00:00:00.484               tiipc_mgr.139281                 slog    133  [IPC] 
Jan 01 00:00:00.484               tiipc_mgr.139281                 slog    133  Mailbox_plugInterrupt: interrupt Number 490, arg 0xEBA6C268

Jan 01 00:00:00.484               tiipc_mgr.139281                 slog      0  Thread Priority set < 10, the value is 1!
Jan 01 00:00:00.518               tiipc_mgr.139281                 slog    133  [IPC] 
Jan 01 00:00:00.518               tiipc_mgr.139281                 slog    133  Mailbox_plugInterrupt: interrupt Number 491, arg 0xEBA6C408

Jan 01 00:00:00.518               tiipc_mgr.139281                 slog      0  Thread Priority set < 10, the value is 1!
Jan 01 00:00:00.551               tiipc_mgr.139281                 slog    133  [IPC] 
Jan 01 00:00:00.551               tiipc_mgr.139281                 slog    133  Mailbox_plugInterrupt: interrupt Number 492, arg 0xEBA6C5A8

Jan 01 00:00:00.551               tiipc_mgr.139281                 slog      0  Thread Priority set < 10, the value is 1!
Jan 01 00:00:00.561              tiudma_mgr.151565                 slog*   131  TI UDMA ResMgr for SOC J721S2 (version=PSDKQNX_08_06_00, date=Fri Nov 15 12:24:27 CST 2024)
Jan 01 00:00:01.213                   iopkt.180239          main_buffer*     0  tcpip starting
Jan 01 00:00:01.213                   iopkt.180239          main_buffer      0  smmu support is disabled
Jan 01 00:00:01.214                   iopkt.180239          main_buffer      0  initializing IPsec...
Jan 01 00:00:01.214                   iopkt.180239          main_buffer      0   done

Jan 01 00:00:01.214                   iopkt.180239          main_buffer      0  IPsec: Initialized Security Association Processing.

Jan 01 00:00:01.236                   iopkt.180239          main_buffer      0  devnp-cpsw2g-main.so mac-to-mac=1,speed=100,ptp=1
Jan 01 00:00:01.237                   iopkt.180239          main_buffer      0  an0

Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog*     0  cpsw_entry:577 Entry -->
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  cpsw_attach:749 Entry -->
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  cpsw_parse_options:239 mac_to_mac -->1
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  cpsw_parse_options:252 speed -->100
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  cpsw_parse_options:227 PTP -->1
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Enable RGMII delay, regData = 0x12
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Success - write to MAIN_ENET_CTRL - 0x12
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Success - write to MAIN CPSW2_CLKSEL - 0x0
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350c0=0x50006 (org=0x50007)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350bc=0x50006 (org=0x50007)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350b8=0x50006 (org=0x50006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350a0=0x50006 (org=0x50006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350a4=0x50006 (org=0x50006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350a8=0x50006 (org=0x50006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350b0=0x50006 (org=0x50006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350ac=0x50006 (org=0x50006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e13508c=0x50006 (org=0x10006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e135090=0x50006 (org=0x10006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e135094=0x50006 (org=0x10006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e135098=0x50006 (org=0x10006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e1350b4=0x50006 (org=0x10006)
Jan 01 00:00:01.237            io_pkt_v4_hc.180239                 slog      0  Pinmux for 0x4e13509c=0x50006 (org=0x10006)
Jan 01 00:00:01.260                   iopkt.180239          main_buffer      0  devnp-cpsw2g.so speed=100
Jan 01 00:00:01.260                   iopkt.180239          main_buffer      0  am0

Jan 01 00:00:01.260            io_pkt_v4_hc.180239                 slog      0  cpsw_entry:577 Entry -->
Jan 01 00:00:01.260            io_pkt_v4_hc.180239                 slog      0  cpsw_attach:749 Entry -->
Jan 01 00:00:01.260            io_pkt_v4_hc.180239                 slog      0  cpsw_parse_options:252 speed -->100
Jan 01 00:00:01.260            io_pkt_v4_hc.180239                 slog      0  Success - write to MCU_ENET_CTRL - 0x12
Jan 01 00:00:01.260            io_pkt_v4_hc.180239                 slog      0  Success - write to MCU_ENET_CLKSEL - 0xf00
Jan 01 00:00:01.306            io_pkt_v4_hc.180239                 slog      0  Enabling clocks!

Jan 01 00:00:01.308            io_pkt_v4_hc.180239                 slog      0  EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:3 From 1 To 0 
Jan 01 00:00:01.308            io_pkt_v4_hc.180239                 slog      0  ENET_CPSW_2G on MAIN NAVSS
Jan 01 00:00:01.309                      console.2                  out*     0  [278551] Jan 01 00:00:01 cron: started
Jan 01 00:00:01.312            io_pkt_v4_hc.180239                 slog     56  [UDMA] Calling Udma_resmgr_open
Jan 01 00:00:01.312            io_pkt_v4_hc.180239                 slog     56  [UDMA] Opening resmgr!!!
Jan 01 00:00:01.312            io_pkt_v4_hc.180239                 slog     56  [UDMA] Opened resmgr fd=6!!!
Jan 01 00:00:01.312            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->vintrNum = 35!!!

Jan 01 00:00:01.312            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->irIntrNum = 11!!!

Jan 01 00:00:01.312            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->coreIntrNum = 75!!!

Jan 01 00:00:01.318         pmic_presetting.278555                 slog*     0  Board_ID = 0xe

Jan 01 00:00:01.318         pmic_presetting.278555                 slog      0  Prepare to Clear PMIC A/B/C Interrupts notification

Jan 01 00:00:01.323            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr2: tx isr 75 thread priority set to 21

Jan 01 00:00:01.323            io_pkt_v4_hc.180239                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/75 coid/1073741849 event/f

Jan 01 00:00:01.323            io_pkt_v4_hc.180239                 slog      0  Enet_open: main.cpsw2g: features: 0x00000002

Jan 01 00:00:01.323            io_pkt_v4_hc.180239                 slog      0  Enet_open: main.cpsw2g: errata  : 0x00000000

Jan 01 00:00:01.324            io_pkt_v4_hc.180239                 slog      0  Mdio_open: MDIO manual mode enabled

Jan 01 00:00:01.324            io_pkt_v4_hc.180239                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x24570fc000, Phys: 0x8fc180000
Jan 01 00:00:01.324            io_pkt_v4_hc.180239                 slog      0  EnetUdma_memMgrInit: addr=0x24570fc000 is  aligned
Jan 01 00:00:01.325         pmic_presetting.278555                 slog      0  Done

Jan 01 00:00:01.325         pmic_presetting.278555                 slog      0  Checking PMIC A settings...

Jan 01 00:00:01.326            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr: some unknown cpsw isr thread priority set to 21

Jan 01 00:00:01.326            io_pkt_v4_hc.180239                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/51 coid/1073741853 event/10

Jan 01 00:00:01.326            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr: some unknown cpsw isr thread priority set to 21

Jan 01 00:00:01.327            io_pkt_v4_hc.180239                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/53 coid/1073741855 event/11

Jan 01 00:00:01.334         pmic_presetting.278555                 slog      0  LDO2 OV/UV threshold error, reset to 5pct. ret=0x3f

Jan 01 00:00:01.340         pmic_presetting.278555                 slog      0  

Jan 01 00:00:01.340         pmic_presetting.278555                 slog      0  Checking PMIC B settings...

Jan 01 00:00:01.340         pmic_presetting.278555                 slog      0  board_id=14

Jan 01 00:00:01.345         pmic_presetting.278555                 slog      0  BULK2 OV/UV threshold error, reset to 5pct. ret=0x3f

Jan 01 00:00:01.347            io_pkt_v4_hc.180239                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x2457198000, Phys: 0x8f9000000
Jan 01 00:00:01.347            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: addr=0x2457198000 is  aligned
Jan 01 00:00:01.347            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: addr=0x2457198000, size=0x2201000, gMem=0x2457198000, gMemBufPhys=0x8f9000000 
Jan 01 00:00:01.347            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: gDmaDescMemArray=0x2457198000, size=0x2000000 
Jan 01 00:00:01.347            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: gRingMemArray=0x2459198000, size=0x201000 
Jan 01 00:00:01.356            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: gDmaDescMemArrayBasePhys=0x8f9000000, gDmaDescMemArrayBase=0x2457198000
Jan 01 00:00:01.358         pmic_presetting.278555                 slog      0  LDO2 OV/UV threshold error, reset to 5pct. ret=0x3f

Jan 01 00:00:01.363         pmic_presetting.278555                 slog      0  

Jan 01 00:00:01.363         pmic_presetting.278555                 slog      0  Checking PMIC C settings...

Jan 01 00:00:01.365         pmic_presetting.278555                 slog      0  

Jan 01 00:00:01.385              fotad_tda4.315418                 slog*     0  TDA4 OTA daemon started.

Jan 01 00:00:01.394            io_pkt_v4_hc.180239                 slog      0  initQs() freePktInfoQ initialized with 3072 pkts
Jan 01 00:00:01.399            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->globalEvent = 34!!!

Jan 01 00:00:01.399            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->vintrNum = 36!!!

Jan 01 00:00:01.399            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->vintrBitNum = 0!!!

Jan 01 00:00:01.399            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->irIntrNum = 12!!!

Jan 01 00:00:01.399            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->coreIntrNum = 76!!!

Jan 01 00:00:01.424            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr2: rx isr 76 thread priority set to 21

Jan 01 00:00:01.424            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/76 coid/1073741856 event/12

Jan 01 00:00:01.425            io_pkt_v4_hc.180239                 slog      0  Host MAC address: 
Jan 01 00:00:01.425            io_pkt_v4_hc.180239                 slog      0  70:ff:76:1d:92:c1
Jan 01 00:00:01.431            io_pkt_v4_hc.180239                 slog      0  EnetIf_Init: 904 Info EnetIf_Init AleBcastEntry status = 0

Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  EnetIf_PtpInit:632 PTP
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  EnetIf_PtpInit:652 CPSW_CPTS_IOCTL_REGISTER_STACK is sucessful
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  cpsw_init:1119 Phy is linked, ifp=0x42119c7680
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Clear IFF_ALLMULTI
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0 
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 1 To 0 
Jan 01 00:00:05.523            io_pkt_v4_hc.180239                 slog      0  ENET_CPSW_2G on MCU NAVSS
Jan 01 00:00:05.527            io_pkt_v4_hc.180239                 slog     56  [UDMA] Calling Udma_resmgr_open
Jan 01 00:00:05.527            io_pkt_v4_hc.180239                 slog     56  [UDMA] Opening resmgr!!!
Jan 01 00:00:05.527            io_pkt_v4_hc.180239                 slog     56  [UDMA] Opened resmgr fd=8!!!
Jan 01 00:00:05.527            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->vintrNum = 37!!!

Jan 01 00:00:05.527            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->irIntrNum = 13!!!

Jan 01 00:00:05.527            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->coreIntrNum = 77!!!

Jan 01 00:00:05.534            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr2: tx isr 77 thread priority set to 21

Jan 01 00:00:05.534            io_pkt_v4_hc.180239                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/77 coid/1073741858 event/13

Jan 01 00:00:05.534            io_pkt_v4_hc.180239                 slog      0  Enet_open: cpsw2g: features: 0x00000002

Jan 01 00:00:05.534            io_pkt_v4_hc.180239                 slog      0  Enet_open: cpsw2g: errata  : 0x00000000

Jan 01 00:00:05.534            io_pkt_v4_hc.180239                 slog      0  Mdio_open: MDIO manual mode enabled

Jan 01 00:00:05.535            io_pkt_v4_hc.180239                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x24626bc000, Phys: 0x8fc4f4000
Jan 01 00:00:05.535            io_pkt_v4_hc.180239                 slog      0  EnetUdma_memMgrInit: addr=0x24626bc000 is  aligned
Jan 01 00:00:05.537            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr: cpsw stat isr thread priority set to 21

Jan 01 00:00:05.537            io_pkt_v4_hc.180239                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/888 coid/1073741862 event/14

Jan 01 00:00:05.537            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr: cpsw cpts isr thread priority set to 22

Jan 01 00:00:05.537            io_pkt_v4_hc.180239                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/890 coid/1073741864 event/15

Jan 01 00:00:05.537            io_pkt_v4_hc.180239                 slog      0  SetPhyConfig: got phy address = 10

Jan 01 00:00:05.669            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)

Jan 01 00:00:05.669            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  EnetPhy_bindDriver: PHY 10: OUI:080028 Model:27 Ver:01 <-> 'dp83tc812'

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_isPhyDevSupported : PHY OUI = 0x80028

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_isPhyDevSupported : PHY MODEL = 0x0027

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_isPhyDevSupported : PHY REVISION = 0x0001

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_isMacModeSupported: mii = 0x0003

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  EnetPhy_bindDriver: PHY 10: OUI:080028 Model:27 Ver:01 <-> 'dp83tc812' : OK

Jan 01 00:00:06.065            io_pkt_v4_hc.180239                 slog      0  EnetPhy_open: PHY 10: open

Jan 01 00:00:06.082            io_pkt_v4_hc.180239                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x2462738000, Phys: 0x83000000
Jan 01 00:00:06.082            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: addr=0x2462738000 is  aligned
Jan 01 00:00:06.082            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: addr=0x2462738000, size=0x2201000, gMem=0x2462738000, gMemBufPhys=0x83000000 
Jan 01 00:00:06.082            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: gDmaDescMemArray=0x2462738000, size=0x2000000 
Jan 01 00:00:06.082            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: gRingMemArray=0x2464738000, size=0x201000 
Jan 01 00:00:06.091            io_pkt_v4_hc.180239                 slog      0  EnetIfMem_init: gDmaDescMemArrayBasePhys=0x83000000, gDmaDescMemArrayBase=0x2462738000
Jan 01 00:00:06.130            io_pkt_v4_hc.180239                 slog      0  initQs() freePktInfoQ initialized with 3072 pkts
Jan 01 00:00:06.134            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->globalEvent = 35!!!

Jan 01 00:00:06.134            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->vintrNum = 38!!!

Jan 01 00:00:06.134            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->vintrBitNum = 1!!!

Jan 01 00:00:06.134            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->irIntrNum = 14!!!

Jan 01 00:00:06.134            io_pkt_v4_hc.180239                 slog     56  [UDMA] eventHandle->coreIntrNum = 78!!!

Jan 01 00:00:06.148            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr2: rx isr 78 thread priority set to 21

Jan 01 00:00:06.148            io_pkt_v4_hc.180239                 slog      0  EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/78 coid/1073741865 event/16

Jan 01 00:00:06.148            io_pkt_v4_hc.180239                 slog      0  Host MAC address: 
Jan 01 00:00:06.148            io_pkt_v4_hc.180239                 slog      0  28:b5:e8:cc:1c:7e
Jan 01 00:00:06.154            io_pkt_v4_hc.180239                 slog      0  EnetIf_Init: 904 Info EnetIf_Init AleBcastEntry status = 0

Jan 01 00:00:07.606            io_pkt_v4_hc.180239                 slog      0  PHY 10 is alive
Jan 01 00:00:09.398             fotad_tc397.323611                 slog*     0  TC397 OTA Daemon Started.

Jan 01 00:00:09.415         rollback_daemon.331804                 slog*     0  Rollback Daemon Started.

Jan 01 00:00:09.415         rollback_daemon.331804                 slog      0  Rollback Daemon Exited.

Jan 01 00:00:10.347            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_reset: PHY 10: global soft-reset

Jan 01 00:00:11.667            io_pkt_v4_hc.180239                 slog      0  IsMaster is 0x0

Jan 01 00:00:12.855            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setNextState: PHY 10: FOUND -> RESET_WAIT (10 ticks)

Jan 01 00:00:13.088            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_isResetComplete: PHY 10: global soft-reset is complete

Jan 01 00:00:13.088            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setNextState: PHY 10: RESET_WAIT -> ENABLE (0 ticks)

Jan 01 00:00:13.189            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: enable

Jan 01 00:00:13.453            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_restart: PHY 10: soft-restart

Jan 01 00:00:13.717            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_setMiiMode: PHY 10: MII mode: 3

Jan 01 00:00:14.509            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_setClkDelay: PHY 10: set delay 0 ps TX, 0 ps RX

Jan 01 00:00:16.093            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_setTxFifoDepth: PHY 10: set FIFO depth 5

Jan 01 00:00:16.357            io_pkt_v4_hc.180239                 slog      0  Dp83tc812_setLedMode: PHY 10: set LED0 = mode0, LED1 = mode0, LED2 = mode1, LED3 = mode0

Jan 01 00:00:16.489            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: req caps: FD100 

Jan 01 00:00:16.621            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: PHY caps: FD100 HD100 

Jan 01 00:00:16.621            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: MAC caps: FD1000 FD100 HD100 FD10 HD10 

Jan 01 00:00:16.621            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: refined caps: FD100 

Jan 01 00:00:16.753            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: PHY is not NWAY-capable

Jan 01 00:00:16.753            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: falling back to manual mode

Jan 01 00:00:16.753            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: new link caps: FD100 

Jan 01 00:00:16.753            io_pkt_v4_hc.180239                 slog      0  EnetPhy_enableState: PHY 10: manual setup

Jan 01 00:00:17.017            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setupManual: PHY 10: requested mode: 100 Mbps full-duplex

Jan 01 00:00:17.017            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setNextState: PHY 10: ENABLE -> LINK_WAIT (50 ticks)

Jan 01 00:00:17.250            io_pkt_v4_hc.180239                 slog      0  EnetPhy_setNextState: PHY 10: LINK_WAIT -> LINKED (0 ticks)

Jan 01 00:00:17.250            io_pkt_v4_hc.180239                 slog      0  Cpsw_isPortLinkUp: Port 1: Sublayer 1 doesn't support link status

Jan 01 00:00:17.250            io_pkt_v4_hc.180239                 slog      0  Cpsw_handleLinkUp: Port 1: Link up: 100-Mbps Full-Duplex

Jan 01 00:00:17.250            io_pkt_v4_hc.180239                 slog      0  cpsw_init:1119 Phy is linked, ifp=0x42119d4500
Jan 01 00:00:17.250            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Clear IFF_ALLMULTI
Jan 01 00:00:17.250            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01
Jan 01 00:00:17.263            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Clear IFF_ALLMULTI
Jan 01 00:00:17.263            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:80:c2:00:00:0e
Jan 01 00:00:17.263            io_pkt_v4_hc.180239                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01
May 27 02:14:57.910                       dumper.4                 slog*     0  run fault pid 180239 tid 5 signal 10 code 3 ip 0x56fc8fd7fc proc/boot/io-pkt-v4-hc
May 27 02:14:57.910                       dumper.4                 slog      0  pid 180239 core file created at /tmp/io-pkt-v4-hc.core

Attached devnp folder after porting SDK10.00.

devnp_sdk10.tar

Please help us to check it.

Thanks.

0 Praveen Rao 18 days ago in reply to Namic Chang

TI__Mastermind 35872 points

Hi Namic,

We did not expect to fail on SDK 10.0, so we are unsure if you are missing other patches from any dependent library linked to the devnp driver.

We'll review the tar file you shared and let you know if anything else is needed. Will get back as soon as we find something by early next week.

Thanks.

0 Namic Chang 14 days ago in reply to Praveen Rao

Prodigy 240 points

Hi Praveen:

I tried to upgrade the codebase to SDK 10.00 and got the same fail for network.

RTOS SDK: ti-processor-sdk-rtos-j721s2-evm-10_00_00_05

QNX SDK: ti-processor-sdk-qnx_800_j721s2_10_00_00_04

QNX Version: 7.1.0

The slog:

eth_error_slog_1119_sdk10.txt

Jan 01 00:00:00.035                       random.5                  low*     0  qcrypto: loading configuration file '/etc/qcrypto.conf' [qcrypto_common.c(190)]
Jan 01 00:00:00.036                    random.5..0                 slog*   700  Random is using the Fortuna PRNG
Jan 01 00:00:00.041                       random.5                  low      0  qcrypto: 'openssl' plugin loaded [qcrypto_plugins.c(354)]
Jan 01 00:00:00.041                    random.5..0                 slog    700  Selecting timer as an entropy source
Jan 01 00:00:00.042                    random.5..0                 slog    700  Registered path names
Jan 01 00:00:00.042                    random.5..0                 slog    700  random: starting resmgr
Jan 01 00:00:00.042                    random.5..0                 slog    700  random: Daemonizing the process
Jan 01 00:00:00.063            devb_sdmmc_am65x.10                 slog*  1800  devb-sdmmc-am65x 1.00A (Jan 31 2023 09:07:28)
Jan 01 00:00:00.063            devb_sdmmc_am65x.10                 slog      0  libcam.so (Sep  3 2021 11:57:38) bver 7010004
Jan 01 00:00:00.064            devb_sdmmc_am65x.10                 slog   1800  sdio_cd:  insertion path 0, cd state 0x1
Jan 01 00:00:00.066            devb_sdmmc_am65x.11                 slog*  1800  devb-sdmmc-am65x 1.00A (Jan 31 2023 09:07:28)
Jan 01 00:00:00.066            devb_sdmmc_am65x.11                 slog      0  libcam.so (Sep  3 2021 11:57:38) bver 7010004
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800  MMC CID:
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    MID 0x45, OID 0x0, PNM DG4008
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    PRV 0x1, PSN 0x359de62f, MDT 2-2024
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800  MMC CSD:
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    CSD_STRUCTURE 3, SPEC_VERS 4, CCC 0x8f5
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    TAAC 15, NSAC 0, TRAN_SPEED 50
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    C_SIZE 4095, C_SIZE_MULT 7
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    READ_BL_LEN 9, WRITE_BL_LEN 9
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    ERASE GRP_SIZE 31, GRP_MULT 31, SIZE 0
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    blksz 512, sectors 2097152, dtr 25000000
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800  MMC EXT CSD:
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    DEVICE_TYPE 0x57, EXT_CSD_REV 8
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    SEC_COUNT 15273600, dtr 200000000
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    HC_ERASE_GRP_SIZE 1, HC_WP_GRP_SIZE 16
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    STROBE 0x1, BKOPS_EN 0x2
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800    Driver type: 0x0
Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog   1800  CFG:  Timing HS200, DTR 200000000, Bus Width 8 bit

Jan 01 00:00:00.148            devb_sdmmc_am65x.10                 slog    100  cam-disk.so (Sep  3 2021 11:57:42)
Jan 01 00:00:00.437               tisci_mgr.110606                 slog*   130  TI SCI ResMgr for SOC J721S2 (version=PSDKQNX_10_00_00, date=Tue Nov 19 07:41:41 UTC 2024)
Jan 01 00:00:00.438               tisci_mgr.110606                 slog      0  InterruptAttachEvent succeed irq/69

Jan 01 00:00:00.438               tisci_mgr.110606                 slog      0  InterruptAttachEvent succeed irq/65

Jan 01 00:00:00.438               tisci_mgr.110606                 slog    130   SYSFW Firmware Version 8.6.3--1-g2249f (Chill Capybara
Jan 01 00:00:00.438               tisci_mgr.110606                 slog    130   SYSFW Firmware revision 0x8
Jan 01 00:00:00.438               tisci_mgr.110606                 slog    130   SYSFW ABI revision 3.1
Jan 01 00:00:00.447          shmemallocator.143373                 slog*   129  TI Shared memory Allocator for SOC J721S2 (version=PSDKQNX_10_00_00, date=Tue Nov 19 07:41:41 UTC 2024)
Jan 01 00:00:00.447          shmemallocator.143373                 slog    129  initSHM:Block[0] @ 0xa8000000 has free-mem = 0x1c00000 - 28 M
Jan 01 00:00:00.447          shmemallocator.143373                 slog    129  initSHM:Block[1] @ 0xe6000000 has free-mem = 0x2000000 - 32 M
Jan 01 00:00:00.463               tiipc_mgr.147471                 slog*   133  TI IPC ResMgr for SOC J721S2 (version=PSDKQNX_10_00_00, date=Tue Nov 19 07:41:41 UTC 2024)
Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  tiipc-mgr: Starting TI IPC Resmgr
Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  tiipc-mgr: Using VRING base address: 0xa8000000, size:0x1c00000
Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8000000, virt 0x4d33f000, len 131072

Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8040000, virt 0x4d35f000, len 131072

Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8020000, virt 0x4d37f000, len 131072

Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8060000, virt 0x4d39f000, len 131072

Jan 01 00:00:00.463               tiipc_mgr.147471                 slog    133  Virtio: remote 1, daTx 0xa8000000, daRx 0xa8040000, prime 0xa8020000

Jan 01 00:00:00.480               tiipc_mgr.147471                 slog    133  Navss Rtr: input 436, output 1051162276400

Jan 01 00:00:00.480               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: Navss Rtr input 436, output 105

Jan 01 00:00:00.480               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: interrupt Number 489, arg 0x455190E8

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog      0  InterruptAttachEvent succeed irq/489

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_MB(1): Self 0 Remote 1 (c0,u0,q0) arg 1,total 1

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8080000, virt 0x4d3c3000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa80c0000, virt 0x4d3e3000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa80a0000, virt 0x4d403000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa80e0000, virt 0x4d423000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Virtio: remote 2, daTx 0xa8080000, daRx 0xa80c0000, prime 0xa80a0000

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_MB(2): Self 0 Remote 2 (c0,u0,q2) arg 2,total 1

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8100000, virt 0x4d443000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8140000, virt 0x4d463000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8120000, virt 0x4d483000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8160000, virt 0x4d4a3000, len 131072

Jan 01 00:00:00.481               tiipc_mgr.147471                 slog    133  Virtio: remote 3, daTx 0xa8100000, daRx 0xa8140000, prime 0xa8120000

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Navss Rtr: input 432, output 1061162276400

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: Navss Rtr input 432, output 106

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: interrupt Number 490, arg 0x45519288

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog      0  InterruptAttachEvent succeed irq/490

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_MB(1): Self 0 Remote 3 (c1,u0,q0) arg 3,total 2

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8180000, virt 0x4d4c4000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa81c0000, virt 0x4d4e4000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa81a0000, virt 0x4d504000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa81e0000, virt 0x4d524000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Virtio: remote 4, daTx 0xa8180000, daRx 0xa81c0000, prime 0xa81a0000

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_MB(2): Self 0 Remote 4 (c1,u0,q2) arg 4,total 2

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8200000, virt 0x4d544000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8240000, virt 0x4d564000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8220000, virt 0x4d584000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8260000, virt 0x4d5a4000, len 131072

Jan 01 00:00:00.498               tiipc_mgr.147471                 slog    133  Virtio: remote 5, daTx 0xa8200000, daRx 0xa8240000, prime 0xa8220000

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Navss Rtr: input 428, output 1071162276400

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: Navss Rtr input 428, output 107

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: interrupt Number 491, arg 0x45519428

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog      0  InterruptAttachEvent succeed irq/491

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Ipc_MB(1): Self 0 Remote 5 (c2,u0,q0) arg 5,total 3

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8280000, virt 0x4d5c5000, len 131072

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa82c0000, virt 0x4d5e5000, len 131072

Jan 01 00:00:00.515               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa82a0000, virt 0x4d605000, len 131072

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa82e0000, virt 0x4d625000, len 131072

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Virtio: remote 6, daTx 0xa8280000, daRx 0xa82c0000, prime 0xa82a0000

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Ipc_MB(2): Self 0 Remote 6 (c2,u0,q2) arg 6,total 3

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8300000, virt 0x4d645000, len 131072

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8340000, virt 0x4d665000, len 131072

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8320000, virt 0x4d685000, len 131072

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8360000, virt 0x4d6a5000, len 131072

Jan 01 00:00:00.516               tiipc_mgr.147471                 slog    133  Virtio: remote 7, daTx 0xa8300000, daRx 0xa8340000, prime 0xa8320000

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Navss Rtr: input 420, output 1081162276400

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: Navss Rtr input 420, output 108

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Mailbox_plugInterrupt: interrupt Number 492, arg 0x455195C8

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog      0  InterruptAttachEvent succeed irq/492

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Ipc_MB(1): Self 0 Remote 7 (c4,u0,q0) arg 7,total 4

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa8380000, virt 0x4d6c6000, len 131072

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa83c0000, virt 0x4d6e6000, len 131072

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa83a0000, virt 0x4d706000, len 131072

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Ipc_addTranslationEntry : phy 0xa83e0000, virt 0x4d726000, len 131072

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Virtio: remote 8, daTx 0xa8380000, daRx 0xa83c0000, prime 0xa83a0000

Jan 01 00:00:00.533               tiipc_mgr.147471                 slog    133  Ipc_MB(2): Self 0 Remote 8 (c4,u0,q2) arg 8,total 4

Jan 01 00:00:00.550              tiudma_mgr.151568                 slog*   131  TI UDMA ResMgr for SOC J721S2 (version=PSDKQNX_10_00_00, date=Tue Nov 19 07:41:41 UTC 2024)
Jan 01 00:00:00.563              tiudma_mgr.151568                 slog      0  InterruptAttachEvent succeed irq/74

Jan 01 00:00:00.575              tiudma_mgr.151568                 slog      0  InterruptAttachEvent succeed irq/485

Jan 01 00:00:01.086                   iopkt.180241          main_buffer*     0  tcpip starting
Jan 01 00:00:01.087                   iopkt.180241          main_buffer      0  smmu support is disabled
Jan 01 00:00:01.088                   iopkt.180241          main_buffer      0  initializing IPsec...
Jan 01 00:00:01.088                   iopkt.180241          main_buffer      0   done

Jan 01 00:00:01.088                   iopkt.180241          main_buffer      0  IPsec: Initialized Security Association Processing.

Jan 01 00:00:01.106                   iopkt.180241          main_buffer      0  devnp-cpsw2g-main.so mac-to-mac=1,speed=100,ptp=1
Jan 01 00:00:01.107                   iopkt.180241          main_buffer      0  an0

Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog*     0  cpsw_entry:577 Entry -->
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  cpsw_attach:751 Entry -->
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  cpsw_parse_options:239 mac_to_mac -->1
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  cpsw_parse_options:252 speed -->100
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  cpsw_parse_options:227 PTP -->1
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Enable RGMII delay, regData = 0x12
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Success - write to MAIN_ENET_CTRL - 0x12
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Success - write to MAIN CPSW2_CLKSEL - 0x0
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240c0=0x50006 (org=0x10006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240bc=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240b8=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240a0=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240a4=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240a8=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240b0=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240ac=0x50006 (org=0x50006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb862408c=0x50006 (org=0x10006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb8624090=0x50006 (org=0x10006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb8624094=0x50006 (org=0x10006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb8624098=0x50006 (org=0x10006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb86240b4=0x50006 (org=0x10006)
Jan 01 00:00:01.107            io_pkt_v4_hc.180241                 slog      0  Pinmux for 0xb862409c=0x50006 (org=0x10006)
Jan 01 00:00:01.129                   iopkt.180241          main_buffer      0  devnp-cpsw2g.so speed=100
Jan 01 00:00:01.129                   iopkt.180241          main_buffer      0  am0

Jan 01 00:00:01.129            io_pkt_v4_hc.180241                 slog      0  cpsw_entry:577 Entry -->
Jan 01 00:00:01.129            io_pkt_v4_hc.180241                 slog      0  cpsw_attach:751 Entry -->
Jan 01 00:00:01.129            io_pkt_v4_hc.180241                 slog      0  cpsw_parse_options:252 speed -->100
Jan 01 00:00:01.129            io_pkt_v4_hc.180241                 slog      0  Success - write to MCU_ENET_CTRL - 0x12
Jan 01 00:00:01.129            io_pkt_v4_hc.180241                 slog      0  Success - write to MCU_ENET_CLKSEL - 0xf00
Jan 01 00:00:01.173            io_pkt_v4_hc.180241                 slog      0  Enabling clocks!

Jan 01 00:00:01.175            io_pkt_v4_hc.180241                 slog      0  EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:3 From 1 To 0 
Jan 01 00:00:01.175            io_pkt_v4_hc.180241                 slog      0  ENET_CPSW_2G on MAIN NAVSS
Jan 01 00:00:01.179            io_pkt_v4_hc.180241                 slog     56  [UDMA] Calling Udma_resmgr_open
Jan 01 00:00:01.179            io_pkt_v4_hc.180241                 slog     56  [UDMA] Opening resmgr!!!
Jan 01 00:00:01.179            io_pkt_v4_hc.180241                 slog     56  [UDMA] Opened resmgr fd=6!!!
Jan 01 00:00:01.179            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->vintrNum = 35!!!

Jan 01 00:00:01.179            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->irIntrNum = 11!!!

Jan 01 00:00:01.179            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->coreIntrNum = 75!!!

Jan 01 00:00:01.180         pmic_presetting.278553                 slog*     0  Board_ID = 0xe

Jan 01 00:00:01.181         pmic_presetting.278553                 slog      0  Prepare to Clear PMIC A/B/C Interrupts notification

Jan 01 00:00:01.184         pmic_presetting.278553                 slog      0  Done

Jan 01 00:00:01.184         pmic_presetting.278553                 slog      0  Checking PMIC A settings...

Jan 01 00:00:01.188            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr2: tx isr 75 thread priority set to 21

Jan 01 00:00:01.188            io_pkt_v4_hc.180241                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/75 coid/1073741849 event/f

Jan 01 00:00:01.188            io_pkt_v4_hc.180241                 slog      0  Enet_open: main.cpsw2g: features: 0x00000002

Jan 01 00:00:01.188            io_pkt_v4_hc.180241                 slog      0  Enet_open: main.cpsw2g: errata  : 0x00000000

Jan 01 00:00:01.188            io_pkt_v4_hc.180241                 slog      0  Mdio_open: MDIO manual mode enabled

Jan 01 00:00:01.189            io_pkt_v4_hc.180241                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x43c15eb000, Phys: 0xbf3180000
Jan 01 00:00:01.189            io_pkt_v4_hc.180241                 slog      0  EnetUdma_memMgrInit: addr=0x43c15eb000 is  aligned
Jan 01 00:00:01.191            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr: some unknown cpsw isr thread priority set to 21

Jan 01 00:00:01.191            io_pkt_v4_hc.180241                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/51 coid/1073741853 event/10

Jan 01 00:00:01.191            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr: some unknown cpsw isr thread priority set to 21

Jan 01 00:00:01.191            io_pkt_v4_hc.180241                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/53 coid/1073741855 event/11

Jan 01 00:00:01.192         pmic_presetting.278553                 slog      0  LDO2 OV/UV threshold error, reset to 5pct. ret=0x3f

Jan 01 00:00:01.198         pmic_presetting.278553                 slog      0  

Jan 01 00:00:01.198         pmic_presetting.278553                 slog      0  Checking PMIC B settings...

Jan 01 00:00:01.198         pmic_presetting.278553                 slog      0  board_id=14

Jan 01 00:00:01.203         pmic_presetting.278553                 slog      0  BULK2 OV/UV threshold error, reset to 5pct. ret=0x3f

Jan 01 00:00:01.211            io_pkt_v4_hc.180241                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x43c1687000, Phys: 0xbf0000000
Jan 01 00:00:01.211            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: addr=0x43c1687000 is  aligned
Jan 01 00:00:01.211            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: addr=0x43c1687000, size=0x2201000, gMem=0x43c1687000, gMemBufPhys=0xbf0000000 
Jan 01 00:00:01.211            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: gDmaDescMemArray=0x43c1687000, size=0x2000000 
Jan 01 00:00:01.211            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: gRingMemArray=0x43c3687000, size=0x201000 
Jan 01 00:00:01.216         pmic_presetting.278553                 slog      0  LDO2 OV/UV threshold error, reset to 5pct. ret=0x3f

Jan 01 00:00:01.220            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: gDmaDescMemArrayBasePhys=0xbf0000000, gDmaDescMemArrayBase=0x43c1687000
Jan 01 00:00:01.222         pmic_presetting.278553                 slog      0  

Jan 01 00:00:01.222         pmic_presetting.278553                 slog      0  Checking PMIC C settings...

Jan 01 00:00:01.224         pmic_presetting.278553                 slog      0  

Jan 01 00:00:01.258            io_pkt_v4_hc.180241                 slog      0  initQs() freePktInfoQ initialized with 3072 pkts
Jan 01 00:00:01.262            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->globalEvent = 34!!!

Jan 01 00:00:01.262            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->vintrNum = 36!!!

Jan 01 00:00:01.262            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->vintrBitNum = 0!!!

Jan 01 00:00:01.262            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->irIntrNum = 12!!!

Jan 01 00:00:01.262            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->coreIntrNum = 76!!!

Jan 01 00:00:01.276            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr2: rx isr 76 thread priority set to 21

Jan 01 00:00:01.276            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/76 coid/1073741856 event/12

Jan 01 00:00:01.276            io_pkt_v4_hc.180241                 slog      0  Host MAC address: 
Jan 01 00:00:01.276            io_pkt_v4_hc.180241                 slog      0  70:ff:76:1d:92:c1
Jan 01 00:00:01.282            io_pkt_v4_hc.180241                 slog      0  EnetIf_Init: 904 Info EnetIf_Init AleBcastEntry status = 0

Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  EnetIf_PtpInit:632 PTP
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  EnetIf_PtpInit:652 CPSW_CPTS_IOCTL_REGISTER_STACK is sucessful
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  cpsw_init:1119 Phy is linked, ifp=0x23ed300680
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Clear IFF_ALLMULTI
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:4 From 1 To 0 
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  EnetIf_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 1 To 0 
Jan 01 00:00:05.374            io_pkt_v4_hc.180241                 slog      0  ENET_CPSW_2G on MCU NAVSS
Jan 01 00:00:05.378            io_pkt_v4_hc.180241                 slog     56  [UDMA] Calling Udma_resmgr_open
Jan 01 00:00:05.378            io_pkt_v4_hc.180241                 slog     56  [UDMA] Opening resmgr!!!
Jan 01 00:00:05.378            io_pkt_v4_hc.180241                 slog     56  [UDMA] Opened resmgr fd=8!!!
Jan 01 00:00:05.378            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->vintrNum = 37!!!

Jan 01 00:00:05.378            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->irIntrNum = 13!!!

Jan 01 00:00:05.378            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->coreIntrNum = 77!!!

Jan 01 00:00:05.385            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr2: tx isr 77 thread priority set to 21

Jan 01 00:00:05.385            io_pkt_v4_hc.180241                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/77 coid/1073741858 event/13

Jan 01 00:00:05.385            io_pkt_v4_hc.180241                 slog      0  Enet_open: cpsw2g: features: 0x00000002

Jan 01 00:00:05.385            io_pkt_v4_hc.180241                 slog      0  Enet_open: cpsw2g: errata  : 0x00000000

Jan 01 00:00:05.385            io_pkt_v4_hc.180241                 slog      0  Mdio_open: MDIO manual mode enabled

Jan 01 00:00:05.386            io_pkt_v4_hc.180241                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x43ccb8b000, Phys: 0xbf34f4000
Jan 01 00:00:05.386            io_pkt_v4_hc.180241                 slog      0  EnetUdma_memMgrInit: addr=0x43ccb8b000 is  aligned
Jan 01 00:00:05.388            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr: cpsw stat isr thread priority set to 21

Jan 01 00:00:05.388            io_pkt_v4_hc.180241                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/888 coid/1073741862 event/14

Jan 01 00:00:05.388            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr: cpsw cpts isr thread priority set to 22

Jan 01 00:00:05.388            io_pkt_v4_hc.180241                 slog      0  EnetIf_CreateISRThread: InterruptAttachEvent succeed irq/890 coid/1073741864 event/15

Jan 01 00:00:05.388            io_pkt_v4_hc.180241                 slog      0  SetPhyConfig: got phy address = 10

Jan 01 00:00:05.520            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)

Jan 01 00:00:05.520            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  EnetPhy_bindDriver: PHY 10: OUI:080028 Model:27 Ver:01 <-> 'dp83tc812'

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_isPhyDevSupported : PHY OUI = 0x80028

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_isPhyDevSupported : PHY MODEL = 0x0027

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_isPhyDevSupported : PHY REVISION = 0x0001

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_isMacModeSupported: mii = 0x0003

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  EnetPhy_bindDriver: PHY 10: OUI:080028 Model:27 Ver:01 <-> 'dp83tc812' : OK

Jan 01 00:00:05.916            io_pkt_v4_hc.180241                 slog      0  EnetPhy_open: PHY 10: open

Jan 01 00:00:05.933            io_pkt_v4_hc.180241                 slog      0  cpsw_alloc:299: Alloc successfull; Virt: 0x43ccc07000, Phys: 0x82000000
Jan 01 00:00:05.933            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: addr=0x43ccc07000 is  aligned
Jan 01 00:00:05.933            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: addr=0x43ccc07000, size=0x2201000, gMem=0x43ccc07000, gMemBufPhys=0x82000000 
Jan 01 00:00:05.933            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: gDmaDescMemArray=0x43ccc07000, size=0x2000000 
Jan 01 00:00:05.933            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: gRingMemArray=0x43cec07000, size=0x201000 
Jan 01 00:00:05.942            io_pkt_v4_hc.180241                 slog      0  EnetIfMem_init: gDmaDescMemArrayBasePhys=0x82000000, gDmaDescMemArrayBase=0x43ccc07000
Jan 01 00:00:05.981            io_pkt_v4_hc.180241                 slog      0  initQs() freePktInfoQ initialized with 3072 pkts
Jan 01 00:00:05.985            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->globalEvent = 35!!!

Jan 01 00:00:05.985            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->vintrNum = 38!!!

Jan 01 00:00:05.985            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->vintrBitNum = 1!!!

Jan 01 00:00:05.985            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->irIntrNum = 14!!!

Jan 01 00:00:05.985            io_pkt_v4_hc.180241                 slog     56  [UDMA] eventHandle->coreIntrNum = 78!!!

Jan 01 00:00:05.999            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr2: rx isr 78 thread priority set to 21

Jan 01 00:00:05.999            io_pkt_v4_hc.180241                 slog      0  EnetIf_registerIntr2: RX InterruptAttachEvent succeed irq/78 coid/1073741865 event/16

Jan 01 00:00:05.999            io_pkt_v4_hc.180241                 slog      0  Host MAC address: 
Jan 01 00:00:05.999            io_pkt_v4_hc.180241                 slog      0  28:b5:e8:cc:1c:7e
Jan 01 00:00:06.005            io_pkt_v4_hc.180241                 slog      0  EnetIf_Init: 904 Info EnetIf_Init AleBcastEntry status = 0

Jan 01 00:00:07.457            io_pkt_v4_hc.180241                 slog      0  PHY 10 is alive
Jan 01 00:00:10.198            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_reset: PHY 10: global soft-reset

Jan 01 00:00:11.518            io_pkt_v4_hc.180241                 slog      0  IsMaster is 0x1

Jan 01 00:00:13.762            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setNextState: PHY 10: FOUND -> RESET_WAIT (10 ticks)

Jan 01 00:00:13.995            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_isResetComplete: PHY 10: global soft-reset is complete

Jan 01 00:00:13.995            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setNextState: PHY 10: RESET_WAIT -> ENABLE (0 ticks)

Jan 01 00:00:14.096            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: enable

Jan 01 00:00:14.360            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_restart: PHY 10: soft-restart

Jan 01 00:00:14.624            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_setMiiMode: PHY 10: MII mode: 3

Jan 01 00:00:15.416            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_setClkDelay: PHY 10: set delay 0 ps TX, 0 ps RX

Jan 01 00:00:17.000            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_setTxFifoDepth: PHY 10: set FIFO depth 5

Jan 01 00:00:17.264            io_pkt_v4_hc.180241                 slog      0  Dp83tc812_setLedMode: PHY 10: set LED0 = mode0, LED1 = mode0, LED2 = mode1, LED3 = mode0

Jan 01 00:00:17.396            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: req caps: FD100 

Jan 01 00:00:17.528            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: PHY caps: FD100 HD100 

Jan 01 00:00:17.528            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: MAC caps: FD1000 FD100 HD100 FD10 HD10 

Jan 01 00:00:17.528            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: refined caps: FD100 

Jan 01 00:00:17.660            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: PHY is not NWAY-capable

Jan 01 00:00:17.660            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: falling back to manual mode

Jan 01 00:00:17.660            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: new link caps: FD100 

Jan 01 00:00:17.660            io_pkt_v4_hc.180241                 slog      0  EnetPhy_enableState: PHY 10: manual setup

Jan 01 00:00:17.924            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setupManual: PHY 10: requested mode: 100 Mbps full-duplex

Jan 01 00:00:17.924            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setNextState: PHY 10: ENABLE -> LINK_WAIT (50 ticks)

Jan 01 00:00:18.157            io_pkt_v4_hc.180241                 slog      0  EnetPhy_setNextState: PHY 10: LINK_WAIT -> LINKED (0 ticks)

Jan 01 00:00:18.157            io_pkt_v4_hc.180241                 slog      0  Cpsw_isPortLinkUp: Port 1: Sublayer 1 doesn't support link status

Jan 01 00:00:18.157            io_pkt_v4_hc.180241                 slog      0  Cpsw_handleLinkUp: Port 1: Link up: 100-Mbps Full-Duplex

Jan 01 00:00:18.157            io_pkt_v4_hc.180241                 slog      0  cpsw_init:1119 Phy is linked, ifp=0x23ed30d500
Jan 01 00:00:18.157            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Clear IFF_ALLMULTI
Jan 01 00:00:18.157            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01
Jan 01 00:00:18.173            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Clear IFF_ALLMULTI
Jan 01 00:00:18.173            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:80:c2:00:00:0e
Jan 01 00:00:18.174            io_pkt_v4_hc.180241                 slog      0  cpsw_filter: Adding Multicast MAC Addr -> 01:00:5e:00:00:01
May 27 02:14:26.455                       dumper.4                 slog*     0  run fault pid 180241 tid 5 signal 10 code 3 ip 0x3abb0277fc proc/boot/io-pkt-v4-hc
May 27 02:14:26.456                       dumper.4                 slog      0  pid 180241 core file created at /tmp/io-pkt-v4-hc.core

Thanks.

0 Praveen Rao 14 days ago in reply to Namic Chang

TI__Mastermind 35872 points

Hi Namic,

Thanks for testing this out on 10.0 and letting us know the result. We need some time to work on this as the team is currently busy with our next 10.1 release.

Please expect a 1-2 weeks delay in responding, mainly because of our release and Thanksgiving holidays.

Thanks.

0 Gibbs Shih 2 days ago in reply to Praveen Rao

TI__Intellectual 2680 points

Hi, Praveen

Namic is my customer.

If anything update, please let us know.

Because it's pending a long time

Thank you very much

Gibbs

0 Praveen Rao 1 day ago in reply to Gibbs Shih

TI__Mastermind 35872 points

Hi Gibbs Shih,

We are looking into this, and we suspect the issue is caused by starting mcu-cpsw2g and main-cpsw2g in the same io-pkt instance. Until the team can reproduce the problem and determine the root cause, we suggest running the drivers in two different instances of io-pkt, like below:

=====

io-pkt-v6-hc -d cpsw2g speed=100 -ptcpip
if_up -p am0
ifconfig -v

io-pkt-v6-hc -d cpsw2g-main speed=100,ptp=1 -ptcpip prefix=/alt
SOCK=/alt if_up -p an0
SOCK=/alt ifconfig -v

=====

Thanks.

Processors

Processors forum

TDA4AL-Q1: Tda4AL cpsw2g / cpsw2g-main crash with heavy network traffic