OMAP3530 GPMC Performance and Throughput

James.Ang said:

Discussion 1:

I read from the TRM that the GPMC has a maximum speed of 100MHz if and only if the L3 Clock is at 100MHz.

But from my investigation, the L3 clock is running at 166MHz instead and this limits the GPMC clock to 83MHz.

I've read from past discussion that the throughput of the ethernet bus is not efficient and is it because of this 83MHz limitation?

That's part of it.  The external device makes a difference too.  I recall hearing of performance differences due to things such as the size of the FIFO integrated into the external Ethernet device.

James.Ang said:

Discussion 2:

In order to use the maximum 100MHz for my FPGA, can the L3 clock be switch on-the-fly without affect other devices that uses the GPMC bus? i.e. the ethernet chip.

My guess is that we cannot do such on-the-fly switching of the L3 clock.  Please enlighten me if this can be done and stable.

Not easily anyways... The L3 interconnect frequency is ALSO the frequency for the LPDDR, so by changing the L3 frequency you would also be changing your LPDDR clock speed.  I imagine you would need to put the LPDDR in self-refresh, change the L3 clock speed, modify the SDRC timings, and then take the SDRC out of self-refresh.  All this code would need to run from internal memory so it would be a royal pain to set it all up.  In short I think I would steer clear!

James.Ang said:

Discussion 3:

How do I model my setup and mathematically estimate the utilization of the GPMC bus?

Assuming the maximum transfer size of 1 R/W cycle for the devices are,

• LAN9221 - Maximum MTU (1500 bytes)
• RAM - 1 page
• ROM - 1 page
• FPGA - 125kbytes

Can't you stick a logic analyzer on there and measure it?  Does your FPGA support chip-scope?

James.Ang said:

Discussion 4:

With multiple devices on the GPMC bus, how does the OMAP does its scheduling when there is a contention to use the GPMC resources?

i.e. Between Ethernet and FPGA

The GPMC is considered a "target" on the L3 interconnect.  The arbitration would happen at the L3 interconnect level.  See the L3 Interconnect chapter of the TRM for starters.

Brad Griffis said:

Discussion 1:

I read from the TRM that the GPMC has a maximum speed of 100MHz if and only if the L3 Clock is at 100MHz.

But from my investigation, the L3 clock is running at 166MHz instead and this limits the GPMC clock to 83MHz.

I've read from past discussion that the throughput of the ethernet bus is not efficient and is it because of this 83MHz limitation?